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| author |  Dinh Nguyen <dinguyen@kernel.org>
| 2020-05-12 13:16:47 -0500 |
|---|---|---|
| committer |  Stephen Boyd <sboyd@kernel.org>
| 2020-05-26 19:13:05 -0700 |
| commit | 80c6b7a0894ffdf3c781f047479752015e5d5b27 (patch) | |
| tree | d39852fa8d8a29b12b0226bce6b53320a3835de2 /drivers/clk/socfpga/Makefile | |
| parent | dt-bindings: documentation: add clock bindings information for Agilex (diff) | |
| download | linux-80c6b7a0894ffdf3c781f047479752015e5d5b27.tar.gz linux-80c6b7a0894ffdf3c781f047479752015e5d5b27.tar.bz2 linux-80c6b7a0894ffdf3c781f047479752015e5d5b27.zip | |
clk: socfpga: agilex: add clock driver for the Agilex platform
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/Makefile')
| -rw-r--r-- | drivers/clk/socfpga/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index ce5aa7802eb8..bf736f8d201a 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o |