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| author |  Emilio López <emilio@elopez.com.ar>
| 2013-12-23 00:32:34 -0300 |
|---|---|---|
| committer | Emilio López <emilio@elopez.com.ar>
| 2013-12-28 17:08:06 -0300 |
| commit | d838ff33ec3a6262f44476d8edc0303acdc16580 (patch) | |
| tree | 0c700acae95db629e0e085bc4608752e4f77b515 /drivers/clk/sunxi | |
| parent | clk: sunxi: clean the magic number of mux parents (diff) | |
| download | linux-d838ff33ec3a6262f44476d8edc0303acdc16580.tar.gz linux-d838ff33ec3a6262f44476d8edc0303acdc16580.tar.bz2 linux-d838ff33ec3a6262f44476d8edc0303acdc16580.zip | |
clk: sunxi: add gating support to PLL1
This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/sunxi')
| -rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index bae5e32c51bd..eeb623bec5ff 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_apb1_config = { }; static const struct factors_data sun4i_pll1_data __initconst = { + .enable = 31, .table = &sun4i_pll1_config, .getter = sun4i_get_pll1_factors, }; static const struct factors_data sun6i_a31_pll1_data __initconst = { + .enable = 31, .table = &sun6i_a31_pll1_config, .getter = sun6i_a31_get_pll1_factors, }; |