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| author |  Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| 2023-08-08 10:27:33 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| 2023-08-15 07:49:24 +0200 |
| commit | 62eef444cf300ea8a5498a98bfcfd6eb0e53dd3e (patch) | |
| tree | 49c3d8575bef8f5fa374e06a9a86b5fae49d99ef /drivers/clk | |
| parent | clk: samsung: exynos5410: do not define number of clocks in bindings (diff) | |
| download | linux-62eef444cf300ea8a5498a98bfcfd6eb0e53dd3e.tar.gz linux-62eef444cf300ea8a5498a98bfcfd6eb0e53dd3e.tar.bz2 linux-62eef444cf300ea8a5498a98bfcfd6eb0e53dd3e.zip | |
clk: samsung: exynos5420: do not define number of clocks in bindings
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 1e0cbf762408..199843f12ae5 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -139,6 +139,9 @@ #define SRC_KFC 0x28200 #define DIV_KFC0 0x28500 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1) + /* Exynos5x SoC type */ enum exynos5x_soc { EXYNOS5420, @@ -1587,7 +1590,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_soc = soc; - ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); + ctx = samsung_clk_init(NULL, reg_base, CLKS_NR); hws = ctx->clk_data.hws; samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, |