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author | 2018-10-18 15:39:08 -0700 | |
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committer | 2018-10-18 15:39:08 -0700 | |
commit | cd8ca3005269ec327643b3cc39681a6fcde16b0d (patch) | |
tree | cc3c259675ad1c038d49e45ec4814ad75ba2c1f1 /drivers/clk | |
parent | Merge branches 'clk-qcom-sdm845-camcc' and 'clk-mtk-unused' into clk-next (diff) | |
parent | clk: mvebu: armada-37xx-periph: add suspend/resume support (diff) | |
parent | Merge tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson into cl... (diff) | |
parent | Merge tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel... (diff) | |
parent | clk: mvebu: ap806: Remove superfluous of_clk_add_provider (diff) | |
parent | clk: davinci: kill davinci_clk_reset_assert/deassert() (diff) | |
download | linux-cd8ca3005269ec327643b3cc39681a6fcde16b0d.tar.gz linux-cd8ca3005269ec327643b3cc39681a6fcde16b0d.tar.bz2 linux-cd8ca3005269ec327643b3cc39681a6fcde16b0d.zip |
Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next
- S2RAM support for Marvell mvebu periph clks
* clk-mvebu-periph-pm:
clk: mvebu: armada-37xx-periph: add suspend/resume support
clk: mvebu: armada-37xx-periph: save the IP base address in the driver data
* clk-meson:
clk: meson: meson8b: use the regmap in the internal reset controller
clk: meson: meson8b: register the clock controller early
clk: meson-axg: pcie: drop the mpll3 clock parent
clk: meson: axg: round audio system master clocks down
clk: meson: clk-pll: drop hard-coded rates from pll tables
clk: meson: clk-pll: remove od parameters
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
clk: meson: clk-pll: add enable bit
* clk-allwinner:
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
clk: sunxi-ng: a64: Add minimal rate for video PLLs
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
clk: sunxi-ng: nkmp: Add constraint for maximum rate
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
clk: sunxi-ng: h6: fix PWM gate/reset offset
clk: sunxi-ng: h6: fix bus clocks' divider position
* clk-mvebu-dup:
clk: mvebu: ap806: Remove superfluous of_clk_add_provider
* clk-davinci:
clk: davinci: kill davinci_clk_reset_assert/deassert()