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author | 2020-11-06 19:27:58 +0800 | |
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committer | 2020-11-13 20:38:52 +1100 | |
commit | 4f07195d638e82a1a1f17f55d7aa8a74dacabfe9 (patch) | |
tree | ecad0f68a68e954b729f54dba949a535a325e768 /drivers/crypto | |
parent | crypto: qat - add support for lm2 and lm3 (diff) | |
download | linux-4f07195d638e82a1a1f17f55d7aa8a74dacabfe9.tar.gz linux-4f07195d638e82a1a1f17f55d7aa8a74dacabfe9.tar.bz2 linux-4f07195d638e82a1a1f17f55d7aa8a74dacabfe9.zip |
crypto: qat - add local memory size to chip info
Add the local memory size to the chip info since the size of this memory
will be different in the next generation of QAT devices.
Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
-rw-r--r-- | drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h | 1 | ||||
-rw-r--r-- | drivers/crypto/qat/qat_common/qat_hal.c | 2 | ||||
-rw-r--r-- | drivers/crypto/qat/qat_common/qat_uclo.c | 2 |
3 files changed, 4 insertions, 1 deletions
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h index 3c587105d09d..0fa5c22fd9c0 100644 --- a/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h +++ b/drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h @@ -26,6 +26,7 @@ struct icp_qat_fw_loader_chip_info { bool sram_visible; bool nn; bool lm2lm3; + u32 lm_size; bool fw_auth; }; diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c index 70fc93f31e79..44cf797ace71 100644 --- a/drivers/crypto/qat/qat_common/qat_hal.c +++ b/drivers/crypto/qat/qat_common/qat_hal.c @@ -699,12 +699,14 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle, handle->chip_info->sram_visible = false; handle->chip_info->nn = true; handle->chip_info->lm2lm3 = false; + handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; handle->chip_info->fw_auth = true; break; case PCI_DEVICE_ID_INTEL_QAT_DH895XCC: handle->chip_info->sram_visible = true; handle->chip_info->nn = true; handle->chip_info->lm2lm3 = false; + handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG; handle->chip_info->fw_auth = false; break; default: diff --git a/drivers/crypto/qat/qat_common/qat_uclo.c b/drivers/crypto/qat/qat_common/qat_uclo.c index 4a90b150199c..32c64a48926f 100644 --- a/drivers/crypto/qat/qat_common/qat_uclo.c +++ b/drivers/crypto/qat/qat_common/qat_uclo.c @@ -311,7 +311,7 @@ static int qat_uclo_init_lmem_seg(struct icp_qat_fw_loader_handle *handle, unsigned int ae; if (qat_uclo_fetch_initmem_ae(handle, init_mem, - ICP_QAT_UCLO_MAX_LMEM_REG, &ae)) + handle->chip_info->lm_size, &ae)) return -EINVAL; if (qat_uclo_create_batch_init_list(handle, init_mem, ae, &obj_handle->lm_init_tab[ae])) |