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author | 2021-01-18 22:44:16 +0800 | |
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committer | 2021-03-23 22:57:41 -0400 | |
commit | 6d9059217a018d6f5bfc4e725cc97288b61dd8be (patch) | |
tree | 009db2c319fb99498ddb0980c0effd4960952971 /drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | |
parent | drm/amdgpu: Enable CP idle interrupts (diff) | |
download | linux-6d9059217a018d6f5bfc4e725cc97288b61dd8be.tar.gz linux-6d9059217a018d6f5bfc4e725cc97288b61dd8be.tar.bz2 linux-6d9059217a018d6f5bfc4e725cc97288b61dd8be.zip |
drm/amdgpu: Fix aldebaran MMHUB CG/LS logic
Aldebaran MMHUB CG/LS logic is controlled by VBIOS. Enable the state
change logic only if driver is used for control.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c index f7471f7d32e1..c3f3e755d4b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c @@ -430,7 +430,7 @@ static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *ad def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { + if (enable) { data |= ATC_L2_MISC_CG__ENABLE_MASK; data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | @@ -481,7 +481,7 @@ static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *ade def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG); - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) + if (enable) data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; else data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; @@ -496,16 +496,15 @@ static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->asic_type) { - case CHIP_ALDEBARAN: + /* Change state only if MCCG support is enabled through driver */ + if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) mmhub_v1_7_update_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); + + /* Change state only if LS support is enabled through driver */ + if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) mmhub_v1_7_update_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE ? true : false); - break; - default: - break; - } + state == AMD_CG_STATE_GATE); return 0; } |