diff options
| author |  Jake Wang <haonan.wang2@amd.com>
| 2021-09-22 14:22:59 -0400 |
|---|---|---|
| committer |  Alex Deucher <alexander.deucher@amd.com>
| 2021-10-19 17:17:16 -0400 |
| commit | 7a28bee067d524c1b8770aa72a82263eb9fc53f0 (patch) | |
| tree | 41b81484ce09ac39553ca230d09eadeb0d2f0a80 /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31 | |
| parent | drm/amd/display: Fully switch to dmub for all dcn21 asics (diff) | |
| download | linux-7a28bee067d524c1b8770aa72a82263eb9fc53f0.tar.gz linux-7a28bee067d524c1b8770aa72a82263eb9fc53f0.tar.bz2 linux-7a28bee067d524c1b8770aa72a82263eb9fc53f0.zip | |
drm/amd/display: Disable dpp root clock when not being used
[Why & How]
Disable root clock for dpp when not being used.
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index d7bf9283dc90..3fae1f1f028d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -219,14 +219,17 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, update_dispclk = true; } - /* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/ if (dpp_clock_lowered) { // increase per DPP DTO before lowering global dppclk + dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); } else { // increase global DPPCLK before lowering per DPP DTO if (update_dppclk || update_dispclk) dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + // always update dtos unless clock is lowered and not safe to lower + if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) + dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); } // notify DMCUB of latest clocks |