diff options
| author |  Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
| 2024-03-22 16:53:14 -0600 |
|---|---|---|
| committer |  Alex Deucher <alexander.deucher@amd.com>
| 2024-04-09 22:07:02 -0400 |
| commit | f3736c0d979a6f9fe2017b864f106dd286a5c18c (patch) | |
| tree | f9287950bd015a893d39fc8da62e0d32da4d9e08 /drivers/gpu/drm/amd/display/dc/clk_mgr | |
| parent | drm/amd/display: Add WBSCL ram coefficient for writeback (diff) | |
| download | linux-f3736c0d979a6f9fe2017b864f106dd286a5c18c.tar.gz linux-f3736c0d979a6f9fe2017b864f106dd286a5c18c.tar.bz2 linux-f3736c0d979a6f9fe2017b864f106dd286a5c18c.zip | |
drm/amd/display: Add code comments clock and encode code
This commit adds some comments to make easier to understand the clock
update for DCN 201, the encode function, and other minor comments.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c index 9c90090e7351..f77840dd051e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c @@ -100,7 +100,15 @@ static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, if (clk_mgr_base->clks.dispclk_khz == 0 || dc->debug.force_clock_mode & 0x1) { + /* this is from resume or boot up, if forced_clock cfg option + * used, we bypass program dispclk and DPPCLK, but need set them + * for S3. + */ + force_reset = true; + /* force_clock_mode 0x1: force reset the clock even it is the + * same clock as long as it is in Passive level. + */ dcn2_read_clocks_from_hw_dentist(clk_mgr_base); } @@ -150,11 +158,14 @@ static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { if (dpp_clock_lowered) { + // if clock is being lowered, increase DTO before lowering refclk dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); dcn20_update_clocks_update_dentist(clk_mgr, context); } else { + // if clock is being raised, increase refclk before lowering DTO if (update_dppclk || update_dispclk) dcn20_update_clocks_update_dentist(clk_mgr, context); + // always update dtos unless clock is lowered and not safe to lower dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); } } |