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| author |  Ilya Bakoulin <ilya.bakoulin@amd.com>
| 2023-09-07 14:03:15 -0400 |
|---|---|---|
| committer |  Alex Deucher <alexander.deucher@amd.com>
| 2023-09-26 17:00:21 -0400 |
| commit | ce74bece80a914deb118bb0a0511a16ad344ffd2 (patch) | |
| tree | d78d8944a1e61c29730e569bbc3c834f7c0af319 /drivers/gpu/drm/amd/display/dc/dcn35 | |
| parent | drm/amd/display: Improve x86 and dmub ips handshake (diff) | |
| download | linux-ce74bece80a914deb118bb0a0511a16ad344ffd2.tar.gz linux-ce74bece80a914deb118bb0a0511a16ad344ffd2.tar.bz2 linux-ce74bece80a914deb118bb0a0511a16ad344ffd2.zip | |
drm/amd/display: Fix DP2.0 timing sync
[Why]
Triggering OTG sync before all OTG/HPO clock programming is complete
causes timing sync to fail and a subsequent P-state hang.
[How]
Move DTB clock programming earlier in the sequence to
enable_stream_timing.
Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn35')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c index 22137fde62bd..addedcfd1238 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c @@ -767,6 +767,7 @@ static const struct dccg_funcs dccg35_funcs = { .set_valid_pixel_rate = dccg35_set_valid_pixel_rate, .enable_symclk_se = dccg35_enable_symclk_se, .disable_symclk_se = dccg35_disable_symclk_se, + .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, }; struct dccg *dccg35_create( |