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| author |  Daniel Miess <daniel.miess@amd.com>
| 2023-11-03 13:52:53 -0400 |
|---|---|---|
| committer |  Alex Deucher <alexander.deucher@amd.com>
| 2024-04-09 21:59:07 -0400 |
| commit | c9c703952600845a3a59ef9670e5b2d037457c81 (patch) | |
| tree | 8c504c7e91656861d01a419d3e4c8d4ff89b1b37 /drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h | |
| parent | drm/amd/display: optimize dml2 pipe resource allocation order (diff) | |
| download | linux-c9c703952600845a3a59ef9670e5b2d037457c81.tar.gz linux-c9c703952600845a3a59ef9670e5b2d037457c81.tar.bz2 linux-c9c703952600845a3a59ef9670e5b2d037457c81.zip | |
drm/amd/display: Toggle additional RCO options in DCN35
[Why]
With root clock optimization now enabled for DCN35 there
are still RCO registers still not being toggled
[How]
Add in logic to toggle RCO registers for DPPCLK,
DPSTREAMCLK and DSCCLK
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h index 09b84307cd9e..135872d88219 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h @@ -31,7 +31,9 @@ #define DPP_REG_LIST_SH_MASK_DCN35(mask_sh) \ DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \ - TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh) + TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh), \ + TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh), \ + TF_SF(DPP_TOP0_DPP_CONTROL, DISPCLK_R_GATE_DISABLE, mask_sh) #define DPP_REG_FIELD_LIST_DCN35(type) \ struct { \ @@ -47,6 +49,11 @@ struct dcn35_dpp_mask { DPP_REG_FIELD_LIST_DCN35(uint32_t); }; +void dpp35_dppclk_control( + struct dpp *dpp_base, + bool dppclk_div, + bool enable); + bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn35_dpp_shift *tf_shift, |