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authorGravatar Ashutosh Dixit <ashutosh.dixit@intel.com> 2022-05-19 09:57:31 +0100
committerGravatar Tvrtko Ursulin <tvrtko.ursulin@intel.com> 2022-05-20 09:11:27 +0100
commitee421bb4cb9535f44015634baad833dcc98c9062 (patch)
tree8827f7c8eaa5dd14fa4c39597e6e4c5b370a2df0 /drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
parentdrm/i915: Introduce has_media_ratio_mode (diff)
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drm/i915/pcode: Extend pcode functions for multiple gt's
Each gt contains an independent instance of pcode. Extend pcode functions to interface with pcode on different gt's. To avoid creating dependency of display functionality on intel_gt, pcode function interfaces are exposed in terms of uncore rather than intel_gt. Callers have been converted to pass in the appropritate (i915 or intel_gt) uncore to the pcode functions. v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo) v3: Retain previous function names to eliminate needless #defines (Rodrigo) v4: Move out i915_pcode_init() to a separate patch (Tvrtko) Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko) Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220519085732.1276255-2-tvrtko.ursulin@linux.intel.com [tursulin: fixup merge conflict]
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 437e96bb3b93..b3fa6607da7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -138,7 +138,7 @@ static int gen6_drpc(struct seq_file *m)
}
if (GRAPHICS_VER(i915) <= 7)
- snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+ snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
seq_printf(m, "RC1e Enabled: %s\n",
str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -559,7 +559,7 @@ static int llc_show(struct seq_file *m, void *data)
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
- snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&ia_freq, NULL);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(rps,