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| author |  Imre Deak <imre.deak@intel.com>
| 2014-03-27 17:45:10 +0200 |
|---|---|---|
| committer |  Daniel Vetter <daniel.vetter@ffwll.ch>
| 2014-04-01 22:58:18 +0200 |
| commit | d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f (patch) | |
| tree | fcc5b97da7ffc2bffc9732c169d8101234b70f1c /drivers/gpu/drm/i915/intel_drv.h | |
| parent | drm/i915: Add PM interrupt details and RPS thresholds to debugfs (diff) | |
| download | linux-d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f.tar.gz linux-d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f.tar.bz2 linux-d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f.zip | |
drm/i915: vlv: cache current CD clock rate
Instead of reading out the CD clock rate from the HW at each modeset, do
this only during driver init and resume and use the cached value during
modeset. This moves things towards a state where the sw and hw side
setup is separated. It's also needed for VLV RPM, where we don't put
device into D0 state until modeset_global_resources is called and thus
can't access any display/gfx registers.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0542de982260..c0146cd65f26 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -665,6 +665,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, const char *intel_output_name(int output); bool intel_has_pending_fb_unpin(struct drm_device *dev); int intel_pch_rawclk(struct drm_device *dev); +int valleyview_cur_cdclk(struct drm_i915_private *dev_priv); void intel_mark_busy(struct drm_device *dev); void intel_mark_fb_busy(struct drm_i915_gem_object *obj, struct intel_ring_buffer *ring); |