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authorGravatar Mikko Perttunen <mperttunen@nvidia.com> 2023-01-19 15:39:00 +0200
committerGravatar Thierry Reding <treding@nvidia.com> 2023-01-26 15:55:38 +0100
commiteb258cc1fd458e584082be987dbc6ec42668c05e (patch)
tree60164f5fcff73ff5f0f5b2d4b280917dbe4aa18f /drivers/gpu/host1x
parentgpu: host1x: Fix mask for syncpoint increment register (diff)
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gpu: host1x: Don't skip assigning syncpoints to channels
The code to write the syncpoint channel assignment register incorrectly skips the write if hypervisor registers are not available. The register, however, is within the guest aperture so remove the check and assign syncpoints properly even on virtualized systems. Fixes: c3f52220f276 ("gpu: host1x: Enable Tegra186 syncpoint protection") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/host1x')
-rw-r--r--drivers/gpu/host1x/hw/syncpt_hw.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c
index dd39d67ccec3..8cf35b2eff3d 100644
--- a/drivers/gpu/host1x/hw/syncpt_hw.c
+++ b/drivers/gpu/host1x/hw/syncpt_hw.c
@@ -106,9 +106,6 @@ static void syncpt_assign_to_channel(struct host1x_syncpt *sp,
#if HOST1X_HW >= 6
struct host1x *host = sp->host;
- if (!host->hv_regs)
- return;
-
host1x_sync_writel(host,
HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff),
HOST1X_SYNC_SYNCPT_CH_APP(sp->id));