diff options
author | 2022-05-17 12:10:46 +0200 | |
---|---|---|
committer | 2022-05-19 15:46:46 +0200 | |
commit | e949dee3625e1b0ef2e40d9aa09c2995281b12f6 (patch) | |
tree | b7ef42d2e8f9b10497c570df00111f6ca7ea00b3 /drivers/mmc/core | |
parent | mmc: sdhci-msm: Reset GCC_SDCC_BCR register for SDHC (diff) | |
download | linux-e949dee3625e1b0ef2e40d9aa09c2995281b12f6.tar.gz linux-e949dee3625e1b0ef2e40d9aa09c2995281b12f6.tar.bz2 linux-e949dee3625e1b0ef2e40d9aa09c2995281b12f6.zip |
mmc: core: Fix busy polling for MMC_SEND_OP_COND again
It turned out that polling period for MMC_SEND_OP_COND, that currently is
set to 1ms, still isn't sufficient. In particular a Micron eMMC on a
Beaglebone platform, is reported to sometimes fail to initialize.
Additional test, shows that extending the period to 4ms is working fine, so
let's make that change.
Reported-by: Jean Rene Dawin <jdawin@math.uni-bielefeld.de>
Tested-by: Jean Rene Dawin <jdawin@math.uni-bielefeld.de>
Fixes: 1760fdb6fe9f (mmc: core: Restore (almost) the busy polling for MMC_SEND_OP_COND")
Fixes: 76bfc7ccc2fa ("mmc: core: adjust polling interval for CMD1")
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20220517101046.27512-1-ulf.hansson@linaro.org
Diffstat (limited to 'drivers/mmc/core')
-rw-r--r-- | drivers/mmc/core/mmc_ops.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 180d7e9d3400..81c55bfd6e0c 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -21,7 +21,7 @@ #define MMC_BKOPS_TIMEOUT_MS (120 * 1000) /* 120s */ #define MMC_SANITIZE_TIMEOUT_MS (240 * 1000) /* 240s */ -#define MMC_OP_COND_PERIOD_US (1 * 1000) /* 1ms */ +#define MMC_OP_COND_PERIOD_US (4 * 1000) /* 4ms */ #define MMC_OP_COND_TIMEOUT_MS 1000 /* 1s */ static const u8 tuning_blk_pattern_4bit[] = { |