diff options
| author |  Rahul Rameshbabu <rrameshbabu@nvidia.com>
| 2023-03-08 08:18:22 -0800 |
|---|---|---|
| committer |  Saeed Mahameed <saeedm@nvidia.com>
| 2023-04-05 18:57:33 -0700 |
| commit | 6a40109275626267ebf413ceda81c64719b5c431 (patch) | |
| tree | 9f783092fcf430afd5fed3c03b4353b00b312590 /drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | |
| parent | net/mlx5e: Remove redundant macsec code (diff) | |
| download | linux-6a40109275626267ebf413ceda81c64719b5c431.tar.gz linux-6a40109275626267ebf413ceda81c64719b5c431.tar.bz2 linux-6a40109275626267ebf413ceda81c64719b5c431.zip | |
net/mlx5: Update cyclecounter shift value to improve ptp free running mode precision
Multiplier values are equivalent to 2^(shift constant) since all mlx5
devices advertise a 1Ghz frequency for the internal timer. The previous
shift constant of 23 led to internal timer adjustments only taking place
when the provided adjustment values were greater than or equal to ~120 ppb
or ~7864 scaled ppm. Using a shift constant of 31 enables adjustments when
an adjustment parameter is greater than or equal to ~0.47 ppb or ~30.8
scaled ppm.
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Reviewed-by: Bar Shapira <bshapira@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 4c9a40211059..932fbc843c69 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -39,7 +39,7 @@ #include "clock.h" enum { - MLX5_CYCLES_SHIFT = 23 + MLX5_CYCLES_SHIFT = 31 }; enum { |