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| author |  Rahul Rameshbabu <rrameshbabu@nvidia.com>
| 2022-10-11 17:28:10 -0700 |
|---|---|---|
| committer |  Saeed Mahameed <saeedm@nvidia.com>
| 2023-01-18 10:34:07 -0800 |
| commit | 8e11a68e2e8abf6510508b75b49ec5953ca262b6 (patch) | |
| tree | aef169b1b407519ba16744b455f73fa68cae09d7 /drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | |
| parent | net/mlx5: Suppress error logging on UCTX creation (diff) | |
| download | linux-8e11a68e2e8abf6510508b75b49ec5953ca262b6.tar.gz linux-8e11a68e2e8abf6510508b75b49ec5953ca262b6.tar.bz2 linux-8e11a68e2e8abf6510508b75b49ec5953ca262b6.zip | |
net/mlx5: Add adjphase function to support hardware-only offset control
The adjtime function supports using hardware to set the clock offset when
the delta was supported by the hardware. When the delta is not supported by
the hardware, the driver handles adjusting the clock. The newly-introduced
adjphase function is similar to the adjtime function, except it guarantees
that a provided clock offset will be used directly by the hardware to
adjust the PTP clock. When the range is not acceptable by the hardware, an
error is returned.
Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 69318b143268..ecdff26a22b0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -326,6 +326,14 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) return 0; } +static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta) +{ + if (delta < S16_MIN || delta > S16_MAX) + return -ERANGE; + + return mlx5_ptp_adjtime(ptp, delta); +} + static int mlx5_ptp_adjfreq_real_time(struct mlx5_core_dev *mdev, s32 freq) { u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {}; @@ -688,6 +696,7 @@ static const struct ptp_clock_info mlx5_ptp_clock_info = { .n_pins = 0, .pps = 0, .adjfine = mlx5_ptp_adjfine, + .adjphase = mlx5_ptp_adjphase, .adjtime = mlx5_ptp_adjtime, .gettimex64 = mlx5_ptp_gettimex, .settime64 = mlx5_ptp_settime, |