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| author |  Petr Machata <petrm@nvidia.com>
| 2023-10-19 12:27:11 +0200 |
|---|---|---|
| committer |  David S. Miller <davem@davemloft.net>
| 2023-10-20 11:47:49 +0100 |
| commit | cf0a86e8ce606438772628c688d1fd36f84ba854 (patch) | |
| tree | 2d58b1ef834519b33edaf88763124bd55a0b5f4a /drivers/net/ethernet/mellanox/mlxsw | |
| parent | mlxsw: reg: Drop SGCR.llb (diff) | |
| download | linux-cf0a86e8ce606438772628c688d1fd36f84ba854.tar.gz linux-cf0a86e8ce606438772628c688d1fd36f84ba854.tar.bz2 linux-cf0a86e8ce606438772628c688d1fd36f84ba854.zip | |
mlxsw: reg: Add SGCR.lag_lookup_pgt_base
Add SGCR.lag_lookup_pgt_base, which is used for configuring the base
address of the LAG table within the PGT table for cases when the driver
is responsible for the table placement.
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index c1da3585c5fb..25b294fdeb3d 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -38,9 +38,18 @@ static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); -static inline void mlxsw_reg_sgcr_pack(char *payload) +/* reg_sgcr_lag_lookup_pgt_base + * Base address used for lookup in PGT table + * Supported when CONFIG_PROFILE.lag_mode = 1 + * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries. + * Access: RW + */ +MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16); + +static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base) { MLXSW_REG_ZERO(sgcr, payload); + mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base); } /* SPAD - Switch Physical Address Register |