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author | 2021-06-06 11:23:41 +0300 | |
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committer | 2021-06-09 17:20:04 -0700 | |
commit | 4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c (patch) | |
tree | 478e718d0fbb1bee9e229246140d669b711ef967 /drivers/net | |
parent | net/mlx5: Consider RoCE cap before init RDMA resources (diff) | |
download | linux-4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c.tar.gz linux-4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c.tar.bz2 linux-4aaf96ac8b45d8e2e019b6b53cce65a73c4ace2c.zip |
net/mlx5: DR, Don't use SW steering when RoCE is not supported
SW steering uses RC QP to write/read to/from ICM, hence it's not
supported when RoCE is not supported as well.
Fixes: 70605ea545e8 ("net/mlx5: DR, Expose APIs for direct rule managing")
Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h index 612b0ac31db2..9737565cd8d4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h @@ -124,10 +124,11 @@ int mlx5dr_action_destroy(struct mlx5dr_action *action); static inline bool mlx5dr_is_supported(struct mlx5_core_dev *dev) { - return MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) || - (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) && - (MLX5_CAP_GEN(dev, steering_format_version) <= - MLX5_STEERING_FORMAT_CONNECTX_6DX)); + return MLX5_CAP_GEN(dev, roce) && + (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) || + (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) && + (MLX5_CAP_GEN(dev, steering_format_version) <= + MLX5_STEERING_FORMAT_CONNECTX_6DX))); } /* buddy functions & structure */ |