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author | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:51 -0600 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-01-13 09:57:51 -0600 |
commit | 2709f0338d4c8cb17e11b448f0257afefae57475 (patch) | |
tree | 1892d2fb65213593d70b6d54a2bacb521dd61739 /drivers/pci/controller/pci-mvebu.c | |
parent | Merge branch 'remotes/lorenzo/pci/xilinx-nwl' (diff) | |
parent | PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device (diff) | |
download | linux-2709f0338d4c8cb17e11b448f0257afefae57475.tar.gz linux-2709f0338d4c8cb17e11b448f0257afefae57475.tar.bz2 linux-2709f0338d4c8cb17e11b448f0257afefae57475.zip |
Merge branch 'remotes/lorenzo/pci/bridge-emul'
- Make emulated ROM BAR read-only by default (Pali Rohár)
- Make some emulated legacy PCI bits read-only for PCIe devices (Pali
Rohár)
- Update reserved bits in emulated PCIe Capability (Pali Rohár)
- Allow drivers to emulate different PCIe Capability versions (Pali Rohár)
- Set emulated Capabilities List bit for all PCIe devices, since they must
have at least a PCIe Capability (Pali Rohár)
* remotes/lorenzo/pci/bridge-emul:
PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
PCI: pci-bridge-emul: Correctly set PCIe capabilities
PCI: pci-bridge-emul: Fix definitions of reserved bits
PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space
PCI: pci-bridge-emul: Make expansion ROM Base Address register read-only
Diffstat (limited to 'drivers/pci/controller/pci-mvebu.c')
-rw-r--r-- | drivers/pci/controller/pci-mvebu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index d7de48c10bda..4f2508dc1ed2 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -723,6 +723,8 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) { struct pci_bridge_emul *bridge = &port->bridge; + u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); + u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); bridge->conf.vendor = PCI_VENDOR_ID_MARVELL; bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; @@ -735,6 +737,12 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; } + /* + * Older mvebu hardware provides PCIe Capability structure only in + * version 1. New hardware provides it in version 2. + */ + bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver); + bridge->has_pcie = true; bridge->data = port; bridge->ops = &mvebu_pci_bridge_emul_ops; |