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author | 2017-02-15 18:48:14 +0530 | |
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committer | 2017-02-21 15:00:26 -0600 | |
commit | 442ec4c04d1235f8c664a74004dae54a7a574d18 (patch) | |
tree | 66e1b54e8cabd635a378b48307175dac998fa47b /drivers/pci/dwc/pcie-armada8k.c | |
parent | PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() (diff) | |
download | linux-442ec4c04d1235f8c664a74004dae54a7a574d18.tar.gz linux-442ec4c04d1235f8c664a74004dae54a7a574d18.tar.bz2 linux-442ec4c04d1235f8c664a74004dae54a7a574d18.zip |
PCI: dwc: all: Split struct pcie_port into host-only and core structures
Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie. This is
in preparation for adding endpoint mode support to designware driver.
While at that also fix checkpatch warnings.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Richard Zhu <hongxing.zhu@nxp.com>
CC: Lucas Stach <l.stach@pengutronix.de>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Minghuan Lian <minghuan.Lian@freescale.com>
CC: Mingkai Hu <mingkai.hu@freescale.com>
CC: Roy Zang <tie-fei.zang@freescale.com>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Niklas Cassel <niklas.cassel@axis.com>
CC: Jesper Nilsson <jesper.nilsson@axis.com>
CC: Joao Pinto <Joao.Pinto@synopsys.com>
CC: Zhou Wang <wangzhou1@hisilicon.com>
CC: Gabriele Paoloni <gabriele.paoloni@huawei.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat (limited to 'drivers/pci/dwc/pcie-armada8k.c')
-rw-r--r-- | drivers/pci/dwc/pcie-armada8k.c | 85 |
1 files changed, 47 insertions, 38 deletions
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c index 5a28dcbf1866..66bac6fbfa9f 100644 --- a/drivers/pci/dwc/pcie-armada8k.c +++ b/drivers/pci/dwc/pcie-armada8k.c @@ -29,7 +29,7 @@ #include "pcie-designware.h" struct armada8k_pcie { - struct pcie_port pp; /* pp.dbi_base is DT ctrl */ + struct dw_pcie *pci; struct clk *clk; }; @@ -67,76 +67,77 @@ struct armada8k_pcie { #define AX_USER_DOMAIN_MASK 0x3 #define AX_USER_DOMAIN_SHIFT 4 -#define to_armada8k_pcie(x) container_of(x, struct armada8k_pcie, pp) +#define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) -static int armada8k_pcie_link_up(struct pcie_port *pp) +static int armada8k_pcie_link_up(struct dw_pcie *pci) { u32 reg; u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; - reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_STATUS_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); if ((reg & mask) == mask) return 1; - dev_dbg(pp->dev, "No link detected (Global-Status: 0x%08x).\n", reg); + dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); return 0; } static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) { - struct pcie_port *pp = &pcie->pp; + struct dw_pcie *pci = pcie->pci; u32 reg; - if (!dw_pcie_link_up(pp)) { + if (!dw_pcie_link_up(pci)) { /* Disable LTSSM state machine to enable configuration */ - reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); reg &= ~(PCIE_APP_LTSSM_EN); - dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } /* Set the device to root complex mode */ - reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); /* Set the PCIe master AxCache attributes */ - dw_pcie_writel_rc(pp, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); - dw_pcie_writel_rc(pp, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); + dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); + dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); /* Set the PCIe master AxDomain attributes */ - reg = dw_pcie_readl_rc(pp, PCIE_ARUSER_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_rc(pp, PCIE_ARUSER_REG, reg); + dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); - reg = dw_pcie_readl_rc(pp, PCIE_AWUSER_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_rc(pp, PCIE_AWUSER_REG, reg); + dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); /* Enable INT A-D interrupts */ - reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_MASK1_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_MASK1_REG, reg); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); - if (!dw_pcie_link_up(pp)) { + if (!dw_pcie_link_up(pci)) { /* Configuration done. Start LTSSM */ - reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG); + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); reg |= PCIE_APP_LTSSM_EN; - dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); } /* Wait until the link becomes active again */ - if (dw_pcie_wait_for_link(pp)) - dev_err(pp->dev, "Link not up after reconfiguration\n"); + if (dw_pcie_wait_for_link(pci)) + dev_err(pci->dev, "Link not up after reconfiguration\n"); } static void armada8k_pcie_host_init(struct pcie_port *pp) { - struct armada8k_pcie *pcie = to_armada8k_pcie(pp); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct armada8k_pcie *pcie = to_armada8k_pcie(pci); dw_pcie_setup_rc(pp); armada8k_pcie_establish_link(pcie); @@ -145,7 +146,7 @@ static void armada8k_pcie_host_init(struct pcie_port *pp) static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) { struct armada8k_pcie *pcie = arg; - struct pcie_port *pp = &pcie->pp; + struct dw_pcie *pci = pcie->pci; u32 val; /* @@ -153,21 +154,21 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) * PCI device. However, they are also latched into the PCIe * controller, so we simply discard them. */ - val = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG); - dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG, val); + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); return IRQ_HANDLED; } -static struct pcie_host_ops armada8k_pcie_host_ops = { - .link_up = armada8k_pcie_link_up, +static struct dw_pcie_host_ops armada8k_pcie_host_ops = { .host_init = armada8k_pcie_host_init, }; static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, struct platform_device *pdev) { - struct pcie_port *pp = &pcie->pp; + struct dw_pcie *pci = pcie->pci; + struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; int ret; @@ -196,10 +197,14 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, return 0; } +static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = armada8k_pcie_link_up, +}; + static int armada8k_pcie_probe(struct platform_device *pdev) { + struct dw_pcie *pci; struct armada8k_pcie *pcie; - struct pcie_port *pp; struct device *dev = &pdev->dev; struct resource *base; int ret; @@ -208,21 +213,25 @@ static int armada8k_pcie_probe(struct platform_device *pdev) if (!pcie) return -ENOMEM; + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev = dev; + pci->ops = &dw_pcie_ops; + pcie->clk = devm_clk_get(dev, NULL); if (IS_ERR(pcie->clk)) return PTR_ERR(pcie->clk); clk_prepare_enable(pcie->clk); - pp = &pcie->pp; - pp->dev = dev; - /* Get the dw-pcie unit configuration/control registers base. */ base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); - pp->dbi_base = devm_ioremap_resource(dev, base); - if (IS_ERR(pp->dbi_base)) { + pci->dbi_base = devm_ioremap_resource(dev, base); + if (IS_ERR(pci->dbi_base)) { dev_err(dev, "couldn't remap regs base %p\n", base); - ret = PTR_ERR(pp->dbi_base); + ret = PTR_ERR(pci->dbi_base); goto fail; } |