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| author |  Atish Patra <atishp@rivosinc.com>
| 2024-04-20 08:17:17 -0700 |
|---|---|---|
| committer |  Anup Patel <anup@brainfault.org>
| 2024-04-22 11:13:42 +0530 |
| commit | d1927f64e0e1094f296842e127138cb5f3bf3c6d (patch) | |
| tree | 26808337043ea2c0cbebc2238f1353533eaa26f7 /drivers/perf | |
| parent | RISCV: KVM: Introduce vcpu->reset_cntx_lock (diff) | |
| download | linux-d1927f64e0e1094f296842e127138cb5f3bf3c6d.tar.gz linux-d1927f64e0e1094f296842e127138cb5f3bf3c6d.tar.bz2 linux-d1927f64e0e1094f296842e127138cb5f3bf3c6d.zip | |
RISC-V: Fix the typo in Scountovf CSR name
The counter overflow CSR name is "scountovf" not "sscountovf".
Fix the csr name.
Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-2-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/riscv_pmu_sbi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8cbe6e5f9c39..3e44d2fb8bf8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,7 +27,7 @@ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \ |