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| author |  Abel Vesa <abel.vesa@linaro.org>
| 2023-02-08 20:00:13 +0200 |
|---|---|---|
| committer |  Vinod Koul <vkoul@kernel.org>
| 2023-02-10 22:28:00 +0530 |
| commit | 354fc6c513ccb459a67c99a57c8d1a837358a001 (patch) | |
| tree | 0003dad11f28df22ac9a480325a0c31b306ea6c5 /drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | |
| parent | phy: qcom-qmp: pcs: Add v6.20 register offsets (diff) | |
| download | linux-354fc6c513ccb459a67c99a57c8d1a837358a001.tar.gz linux-354fc6c513ccb459a67c99a57c8d1a837358a001.tar.bz2 linux-354fc6c513ccb459a67c99a57c8d1a837358a001.zip | |
phy: qcom-qmp: pcs-pcie: Add v6 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated
header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h')
0 files changed, 0 insertions, 0 deletions