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authorGravatar Linus Torvalds <torvalds@linux-foundation.org> 2023-11-03 19:06:12 -1000
committerGravatar Linus Torvalds <torvalds@linux-foundation.org> 2023-11-03 19:06:12 -1000
commitbfafa2c19d706ab1db0b581f9d3886469fab8627 (patch)
treeb45ebc453e3859b49469c2b56dfb51eedbbe9d87 /drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
parentMerge tag 'dmaengine-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/gi... (diff)
parentphy: Remove duplicated include in phy-ralink-usb.c (diff)
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Merge tag 'phy-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull generic phy updates from Vinod Koul: "New Support: - Qualcomm sa8775p qmp-pcie, IPQ5018, and SC7280 qmp-ufs support - Mediatek MT8188 support Updates: - Device tree device_get_match_data() usage and dropping of_match_device() calls - Qualcomm qmp usb and combo phy updates for v6 register layout - Qualcomm eusb2-repeater updates for tuning overrides, regmap fields - STih407 usb binding and ralink usb-phy yaml conversion - renesas r8a779f0 serdes init sequencing updates" * tag 'phy-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (32 commits) phy: Remove duplicated include in phy-ralink-usb.c phy: Kconfig: Select GENERIC_PHY for GENERIC_PHY_MIPI_DPHY phy: qcom-qmp-pcie: add endpoint support for sa8775p dt-bindings: phy: ralink-usb-phy: convert to dtschema dt-bindings: phy: Convert PXA1928 USB/HSIC PHY to DT schema phy: Drop unnecessary of_match_device() calls phy: rockchip-inno-usb2: Drop unnecessary DT includes phy: Use device_get_match_data() phy: realtek: Replace of_device.h with explicit includes phy: renesas: r8a779f0-ether-serdes: Add .exit() ops phy: renesas: r8a779f0-ether-serdes: Reset in .init() phy: qcom-qmp-combo: use v6 registers in v6 regs layout phy: qcom-qmp-usb: move PCS v6 register to the proper header phy: qcom-qmp-combo: fix the prefix for the PCS_USB v6 registers phy: sun4i-usb: update array size phy: qualcomm: phy-qcom-eusb2-repeater: Add tuning overrides phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fields dt-bindings: phy: qcom,snps-eusb2-repeater: Add magic tuning overrides dt-bindings: phy: Add compatible for Mediatek MT8188 ...
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h')
-rw-r--r--drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h29
1 files changed, 7 insertions, 22 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
index c38530d6776b..df670143feb1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h
@@ -6,27 +6,12 @@
#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_
#define QCOM_PHY_QMP_PCS_USB_V6_H_
-/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
-#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4
-#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8
-#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc
-#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8
-#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
-#define QPHY_USB_V6_PCS_POWER_STATE_CONFIG1 0x90
-#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188
-#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
-#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
-#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0
-#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0
-#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4
-#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
-#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc
-#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec
-
-#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x00
-#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
-#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
-#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
-#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
+#define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1 0x00
+#define QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
+#define QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
+#define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
+#define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
+#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+#define QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
#endif