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| author |  Johan Hovold <johan+linaro@kernel.org>
| 2022-06-09 14:03:36 +0200 |
|---|---|---|
| committer |  Vinod Koul <vkoul@kernel.org>
| 2022-07-05 12:42:32 +0530 |
| commit | 74acf0ee6eaafd7c44c34e379cdd45549fc57057 (patch) | |
| tree | 0adb6d8cce6b3a3d73bac196ff33d34ed2aaed18 /drivers/phy | |
| parent | phy: qcom-qmp-usb: clean up pipe clock handling (diff) | |
| download | linux-74acf0ee6eaafd7c44c34e379cdd45549fc57057.tar.gz linux-74acf0ee6eaafd7c44c34e379cdd45549fc57057.tar.bz2 linux-74acf0ee6eaafd7c44c34e379cdd45549fc57057.zip | |
phy: qcom-qmp: clean up v4 and v5 define order
Clean up the QMP v4 and v5 defines by moving a few entries that were out
of order.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220609120338.4080-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 06b2556ed93a..10329ce9497a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -577,8 +577,8 @@ #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 -#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 @@ -1093,8 +1093,8 @@ #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 -#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 @@ -1121,8 +1121,8 @@ #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 -#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc /* Only for QMP V5 PHY - TX registers */ #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 |