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| author |  Johnny Huang <johnny_huang@aspeedtech.com>
| 2019-12-02 16:44:31 +1030 |
|---|---|---|
| committer |  Linus Walleij <linus.walleij@linaro.org>
| 2019-12-13 09:40:37 +0100 |
| commit | 5f52c853847ffdc9654e5b685e1a1ae5bee83e65 (patch) | |
| tree | 39f05f901bf1f17777376e1f9c8648621cfa44bb /drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | |
| parent | pinctrl: aspeed: Move aspeed_pin_config_map to separate source file (diff) | |
| download | linux-5f52c853847ffdc9654e5b685e1a1ae5bee83e65.tar.gz linux-5f52c853847ffdc9654e5b685e1a1ae5bee83e65.tar.bz2 linux-5f52c853847ffdc9654e5b685e1a1ae5bee83e65.zip | |
pinctrl: aspeed: Use masks to describe pinconf bitfields
Since some of the AST2600 pinconf setting are not just single bit, modified
aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to
support configuring multiple bits.
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
[AJ: Tweak commit message]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191202061432.3996-7-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 2acbcf3d508a..0cab4c2576e2 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2781,11 +2781,11 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, } static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, - { PIN_CONFIG_BIAS_DISABLE, -1, 1}, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, }; static const struct aspeed_pinmux_ops aspeed_g5_ops = { |