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author | 2020-01-29 09:51:36 -0800 | |
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committer | 2020-01-29 09:51:36 -0800 | |
commit | 6ba3d7066c71d2103da255df19eb613d299bab15 (patch) | |
tree | 43f2bccb85638b7e6f7fde6a5ca7ae6a4e718c35 /drivers/pinctrl/meson | |
parent | Merge tag 'gpio-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linu... (diff) | |
parent | pinctrl: madera: Remove extra blank line (diff) | |
download | linux-6ba3d7066c71d2103da255df19eb613d299bab15.tar.gz linux-6ba3d7066c71d2103da255df19eb613d299bab15.tar.bz2 linux-6ba3d7066c71d2103da255df19eb613d299bab15.zip |
Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes, nothing too exciting about
this.
Some changes hit arch/sh and arch/arm but are well isolated and
acknowledged by the respective arch maintainers.
Core changes:
- Dropped the chained IRQ setup callback into GPIOLIB as we got rid
of the last users of that in this changeset.
New drivers:
- New driver for Ingenic X1830.
- New driver for Freescale i.MX8MP.
Driver enhancements:
- Fix all remaining Intel drivers to pass their IRQ chips along with
the GPIO chips.
- Intel Baytrail allocates its irqchip dynamically.
- Intel Lynxpoint is thoroughly rewritten and modernized.
- Aspeed AST2600 pin muxing and configuration is much improved.
- Qualcomm SC7180 functions are updated and wakeup interrupt map is
provided.
- A whole slew of Renesas SH-PFC cleanups and improvements.
- Fix up the Intel DT bindings to use the generic YAML DT bindings
schema (a first user of this)"
* tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
pinctrl: madera: Remove extra blank line
pinctrl: qcom: Don't lock around irq_set_irq_wake()
pinctrl: mvebu: armada-37xx: use use platform api
gpio: Drop the chained IRQ handler assign function
pinctrl: freescale: Add i.MX8MP pinctrl driver support
dt-bindings: imx: Add pinctrl binding doc for i.MX8MP
pinctrl: tigerlake: Tiger Lake uses _HID enumeration
pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID
pinctrl: iproc: Use platform_get_irq_optional() to avoid error message
pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema
pinctrl: intel: Pass irqchip when adding gpiochip
pinctrl: intel: Add GPIO <-> pin mapping ranges via callback
pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output
pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins
pinctrl: sunrisepoint: Add missing Interrupt Status register offset
pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers
pinctrl: artpec6: fix __iomem on reg in set
pinctrl: ingenic: Use devm_platform_ioremap_resource()
pinctrl: ingenic: Factorize irq_set_type function
pinctrl: ingenic: Remove duplicated ingenic_chip_info structures
...
Diffstat (limited to 'drivers/pinctrl/meson')
-rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h | 2 | ||||
-rw-r--r-- | drivers/pinctrl/meson/pinctrl-meson8b.c | 7 |
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h index 8ff88bf2e849..aa79d7ecee00 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ /* * Copyright (c) 2017 Baylibre SAS. * Author: Jerome Brunet <jbrunet@baylibre.com> @@ -5,7 +6,6 @@ * Copyright (c) 2017 Amlogic, Inc. All rights reserved. * Author: Xingyu Chen <xingyu.chen@amlogic.com> * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) */ struct meson_pmx_bank { diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 2d5339edd0b7..6cd4b3ec1b40 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -233,6 +233,8 @@ static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 }; static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 }; static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 }; +static const unsigned int eth_rxd3_h_pins[] = { GPIOH_5 }; +static const unsigned int eth_rxd2_h_pins[] = { GPIOH_6 }; static const unsigned int clk_24m_out_pins[] = { GPIOH_9 }; static const unsigned int spi_ss1_pins[] = { GPIOH_0 }; @@ -535,6 +537,8 @@ static struct meson_pmx_group meson8b_cbus_groups[] = { GROUP(spi_miso_1, 9, 12), GROUP(spi_mosi_1, 9, 11), GROUP(spi_sclk_1, 9, 10), + GROUP(eth_rxd3_h, 6, 15), + GROUP(eth_rxd2_h, 6, 14), GROUP(eth_txd3, 6, 13), GROUP(eth_txd2, 6, 12), GROUP(eth_tx_clk, 6, 11), @@ -746,7 +750,8 @@ static const char * const ethernet_groups[] = { "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1", "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv", "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk", - "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2" + "eth_txd2", "eth_txd3", "eth_rxd3", "eth_rxd2", + "eth_rxd3_h", "eth_rxd2_h" }; static const char * const i2c_a_groups[] = { |