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authorGravatar Stefan Agner <stefan@agner.ch> 2018-07-26 17:40:24 +0200
committerGravatar Linus Walleij <linus.walleij@linaro.org> 2018-07-29 23:37:03 +0200
commit3c94d2d08a032d911bbe34f2edb24cb63a63644a (patch)
treeb004755fe7335a3c3e4469758e452606a6ff7e07 /drivers/pinctrl/tegra/pinctrl-tegra.h
parentpinctrl: intel: Do pin translation when lock IRQ (diff)
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pinctrl: tegra: define GPIO compatible node per SoC
Tegra 2 uses a different GPIO controller which uses "tegra20-gpio" as compatible string. Make the compatible string the GPIO node is using a SoC specific property. This prevents the kernel from registering the GPIO range twice in case the GPIO range is specified in the device tree. Fixes: 9462510ce31e ("pinctrl: tegra: Only set the gpio range if needed") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/tegra/pinctrl-tegra.h')
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index aa33c20766c4..44c71941b5f8 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -189,6 +189,7 @@ struct tegra_pingroup {
*/
struct tegra_pinctrl_soc_data {
unsigned ngpios;
+ const char *gpio_compatible;
const struct pinctrl_pin_desc *pins;
unsigned npins;
struct tegra_function *functions;