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| author |  Krishna Yarlagadda <kyarlagadda@nvidia.com>
| 2019-05-16 17:23:12 +0530 |
|---|---|---|
| committer |  Linus Walleij <linus.walleij@linaro.org>
| 2019-06-01 19:21:57 +0200 |
| commit | b4e18ba27e22f63098759afab3d804a5a06489c2 (patch) | |
| tree | 76d1c63769720183aa79585fe489fb9b8ee5818c /drivers/pinctrl/tegra/pinctrl-tegra.h | |
| parent | pinctrl: Add Tegra194 pinctrl DT bindings (diff) | |
| download | linux-b4e18ba27e22f63098759afab3d804a5a06489c2.tar.gz linux-b4e18ba27e22f63098759afab3d804a5a06489c2.tar.bz2 linux-b4e18ba27e22f63098759afab3d804a5a06489c2.zip | |
pinctrl: tegra: Support 32 bit register access
Tegra194 chip has 32 bit pinctrl registers. Existing register defines in
header are only 16 bit.
Modified common pinctrl-tegra driver to support 32 bit registers of
Tegra 194 and later chips.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/tegra/pinctrl-tegra.h')
| -rw-r--r-- | drivers/pinctrl/tegra/pinctrl-tegra.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 44c71941b5f8..82cd947e5171 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -143,10 +143,10 @@ struct tegra_pingroup { const unsigned *pins; u8 npins; u8 funcs[4]; - s16 mux_reg; - s16 pupd_reg; - s16 tri_reg; - s16 drv_reg; + s32 mux_reg; + s32 pupd_reg; + s32 tri_reg; + s32 drv_reg; u32 mux_bank:2; u32 pupd_bank:2; u32 tri_bank:2; |