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author | 2020-05-15 15:06:00 +0200 | |
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committer | 2020-05-15 15:06:00 +0200 | |
commit | 98a09fb4cbb0b1a750259c285b3abe7e67717121 (patch) | |
tree | 7d7f495990d298fceed61ca69f1ad576c0fd0d60 /drivers/pinctrl | |
parent | pinctrl: rockchip: fix memleak in rockchip_dt_node_to_map (diff) | |
parent | pinctrl: intel: Move npins closer to pin_base in struct intel_community (diff) | |
download | linux-98a09fb4cbb0b1a750259c285b3abe7e67717121.tar.gz linux-98a09fb4cbb0b1a750259c285b3abe7e67717121.tar.bz2 linux-98a09fb4cbb0b1a750259c285b3abe7e67717121.zip |
Merge tag 'intel-pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.8-1
* Introduce GPIO driver for Jasper Lake
* Fix long standing bug in Sunrisepoint-H PAD locking code
* Enable pin configuration setting for GPIO chip for Baytrail
* Work around race condition in Cherriview hardware when handle IRQ
* Clean up Cherryview code to be closer to other drivers
The following is an automated git shortlog grouped by driver:
baytrail:
- Use platform_get_irq_optional() explicitly
- Enable pin configuration setting for GPIO chip
cannonlake:
- Use generic flag for special GPIO base treatment
cherryview:
- Add missing spinlock usage in chv_gpio_irq_handler
- Use GENMASK() consistently
- Re-use data structures from pinctrl-intel.h (part 2)
icelake:
- Use generic flag for special GPIO base treatment
intel:
- Move npins closer to pin_base in struct intel_community
- Update description in struct intel_community
- Add Intel Jasper Lake pin controller support
- Introduce new flag to force GPIO base to be 0
- Introduce common flags for GPIO mapping scheme
lynxpoint:
- Use platform_get_irq_optional() explicitly
sunrisepoint:
- Fix PAD lock register offset for SPT-H
tigerlake:
- Use generic flag for special GPIO base treatment
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r-- | drivers/pinctrl/intel/Kconfig | 8 | ||||
-rw-r--r-- | drivers/pinctrl/intel/Makefile | 1 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-baytrail.c | 10 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-cannonlake.c | 58 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 282 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-icelake.c | 30 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.c | 22 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.h | 27 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-jasperlake.c | 344 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-lynxpoint.c | 10 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 15 | ||||
-rw-r--r-- | drivers/pinctrl/intel/pinctrl-tigerlake.c | 32 |
12 files changed, 573 insertions, 266 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index ee440ec4c94c..787833e343a4 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -111,6 +111,14 @@ config PINCTRL_ICELAKE This pinctrl driver provides an interface that allows configuring of Intel Ice Lake PCH pins and using them as GPIOs. +config PINCTRL_JASPERLAKE + tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Jasper Lake PCH pins and using them as GPIOs. + config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index f60f99cfa7aa..f6f63eb8100f 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o +obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index b409642f168d..0ff7c55173da 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1286,6 +1286,7 @@ static const struct gpio_chip byt_gpio_chip = { .direction_output = byt_gpio_direction_output, .get = byt_gpio_get, .set = byt_gpio_set, + .set_config = gpiochip_generic_config, .dbg_show = byt_gpio_dbg_show, }; @@ -1505,8 +1506,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) { struct platform_device *pdev = to_platform_device(vg->dev); struct gpio_chip *gc; - struct resource *irq_rc; - int ret; + int irq, ret; /* Set up gpio chip */ vg->chip = byt_gpio_chip; @@ -1526,8 +1526,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) #endif /* set up interrupts */ - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq_rc && irq_rc->start) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { struct gpio_irq_chip *girq; vg->irqchip.name = "BYT-GPIO", @@ -1547,7 +1547,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned int)irq_rc->start; + girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index f51b27bbf9f1..515f57a0d180 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -30,8 +30,6 @@ .gpio_base = (g), \ } -#define CNL_NO_GPIO -1 - #define CNL_COMMUNITY(b, s, e, o, g) \ { \ .barno = (b), \ @@ -377,27 +375,27 @@ static const struct intel_padgroup cnlh_community0_gpps[] = { }; static const struct intel_padgroup cnlh_community1_gpps[] = { - CNL_GPP(0, 51, 74, 64), /* GPP_C */ - CNL_GPP(1, 75, 98, 96), /* GPP_D */ - CNL_GPP(2, 99, 106, 128), /* GPP_G */ - CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */ - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ - CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */ + CNL_GPP(0, 51, 74, 64), /* GPP_C */ + CNL_GPP(1, 75, 98, 96), /* GPP_D */ + CNL_GPP(2, 99, 106, 128), /* GPP_G */ + CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ + CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ + CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ }; static const struct intel_padgroup cnlh_community3_gpps[] = { - CNL_GPP(0, 155, 178, 192), /* GPP_K */ - CNL_GPP(1, 179, 202, 224), /* GPP_H */ - CNL_GPP(2, 203, 215, 256), /* GPP_E */ - CNL_GPP(3, 216, 239, 288), /* GPP_F */ - CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */ + CNL_GPP(0, 155, 178, 192), /* GPP_K */ + CNL_GPP(1, 179, 202, 224), /* GPP_H */ + CNL_GPP(2, 203, 215, 256), /* GPP_E */ + CNL_GPP(3, 216, 239, 288), /* GPP_F */ + CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnlh_community4_gpps[] = { - CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */ - CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */ - CNL_GPP(2, 269, 286, 320), /* GPP_I */ - CNL_GPP(3, 287, 298, 352), /* GPP_J */ + CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ + CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + CNL_GPP(2, 269, 286, 320), /* GPP_I */ + CNL_GPP(3, 287, 298, 352), /* GPP_J */ }; static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; @@ -790,25 +788,25 @@ static const struct intel_function cnllp_functions[] = { }; static const struct intel_padgroup cnllp_community0_gpps[] = { - CNL_GPP(0, 0, 24, 0), /* GPP_A */ - CNL_GPP(1, 25, 50, 32), /* GPP_B */ - CNL_GPP(2, 51, 58, 64), /* GPP_G */ - CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */ + CNL_GPP(0, 0, 24, 0), /* GPP_A */ + CNL_GPP(1, 25, 50, 32), /* GPP_B */ + CNL_GPP(2, 51, 58, 64), /* GPP_G */ + CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnllp_community1_gpps[] = { - CNL_GPP(0, 68, 92, 96), /* GPP_D */ - CNL_GPP(1, 93, 116, 128), /* GPP_F */ - CNL_GPP(2, 117, 140, 160), /* GPP_H */ - CNL_GPP(3, 141, 172, 192), /* vGPIO */ - CNL_GPP(4, 173, 180, 224), /* vGPIO */ + CNL_GPP(0, 68, 92, 96), /* GPP_D */ + CNL_GPP(1, 93, 116, 128), /* GPP_F */ + CNL_GPP(2, 117, 140, 160), /* GPP_H */ + CNL_GPP(3, 141, 172, 192), /* vGPIO */ + CNL_GPP(4, 173, 180, 224), /* vGPIO */ }; static const struct intel_padgroup cnllp_community4_gpps[] = { - CNL_GPP(0, 181, 204, 256), /* GPP_C */ - CNL_GPP(1, 205, 228, 288), /* GPP_E */ - CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */ - CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */ + CNL_GPP(0, 181, 204, 256), /* GPP_C */ + CNL_GPP(1, 205, 228, 288), /* GPP_E */ + CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ }; static const struct intel_community cnllp_communities[] = { diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 4c74fdde576d..8e3953a223d0 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -35,18 +35,18 @@ #define CHV_PADCTRL0 0x000 #define CHV_PADCTRL0_INTSEL_SHIFT 28 -#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) +#define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) #define CHV_PADCTRL0_TERM_UP BIT(23) #define CHV_PADCTRL0_TERM_SHIFT 20 -#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) +#define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) #define CHV_PADCTRL0_TERM_20K 1 #define CHV_PADCTRL0_TERM_5K 2 #define CHV_PADCTRL0_TERM_1K 4 #define CHV_PADCTRL0_PMODE_SHIFT 16 -#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) +#define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) #define CHV_PADCTRL0_GPIOEN BIT(15) #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 -#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) +#define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) #define CHV_PADCTRL0_GPIOCFG_GPIO 0 #define CHV_PADCTRL0_GPIOCFG_GPO 1 #define CHV_PADCTRL0_GPIOCFG_GPI 2 @@ -57,58 +57,17 @@ #define CHV_PADCTRL1 0x004 #define CHV_PADCTRL1_CFGLOCK BIT(31) #define CHV_PADCTRL1_INVRXTX_SHIFT 4 -#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) -#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) +#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) +#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) +#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) #define CHV_PADCTRL1_ODEN BIT(3) -#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) -#define CHV_PADCTRL1_INTWAKECFG_MASK 7 +#define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 /** - * struct chv_alternate_function - A per group or per pin alternate function - * @pin: Pin number (only used in per pin configs) - * @mode: Mode the pin should be set in - * @invert_oe: Invert OE for this pin - */ -struct chv_alternate_function { - unsigned int pin; - u8 mode; - bool invert_oe; -}; - -/** - * struct chv_pincgroup - describes a CHV pin group - * @name: Name of the group - * @pins: An array of pins in this group - * @npins: Number of pins in this group - * @altfunc: Alternate function applied to all pins in this group - * @overrides: Alternate function override per pin or %NULL if not used - * @noverrides: Number of per pin alternate function overrides if - * @overrides != NULL. - */ -struct chv_pingroup { - const char *name; - const unsigned int *pins; - size_t npins; - struct chv_alternate_function altfunc; - const struct chv_alternate_function *overrides; - size_t noverrides; -}; - -/** - * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs - * @base: Start pin number - * @npins: Number of pins in this range - */ -struct chv_gpio_pinrange { - unsigned int base; - unsigned int npins; -}; - -/** * struct chv_community - A community specific configuration * @uid: ACPI _UID used to match the community * @pins: All pins in this community @@ -117,8 +76,8 @@ struct chv_gpio_pinrange { * @ngroups: Number of groups * @functions: All functions in this community * @nfunctions: Number of functions - * @gpio_ranges: An array of GPIO ranges in this community - * @ngpio_ranges: Number of GPIO ranges + * @gpps: Pad groups + * @ngpps: Number of pad groups in this community * @nirqs: Total number of IRQs this community can generate * @acpi_space_id: An address space ID for ACPI OpRegion handler */ @@ -126,12 +85,12 @@ struct chv_community { const char *uid; const struct pinctrl_pin_desc *pins; size_t npins; - const struct chv_pingroup *groups; + const struct intel_pingroup *groups; size_t ngroups; const struct intel_function *functions; size_t nfunctions; - const struct chv_gpio_pinrange *gpio_ranges; - size_t ngpio_ranges; + const struct intel_padgroup *gpps; + size_t ngpps; size_t nirqs; acpi_adr_space_type acpi_space_id; }; @@ -173,37 +132,14 @@ struct chv_pinctrl { struct chv_pin_context *saved_pin_context; }; -#define ALTERNATE_FUNCTION(p, m, i) \ - { \ - .pin = (p), \ - .mode = (m), \ - .invert_oe = (i), \ - } - -#define PIN_GROUP_WITH_ALT(n, p, m, i) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .altfunc.mode = (m), \ - .altfunc.invert_oe = (i), \ - } +#define PINMODE_INVERT_OE BIT(15) -#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .altfunc.mode = (m), \ - .altfunc.invert_oe = (i), \ - .overrides = (o), \ - .noverrides = ARRAY_SIZE((o)), \ - } +#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) -#define GPIO_PINRANGE(start, end) \ +#define CHV_GPP(start, end) \ { \ .base = (start), \ - .npins = (end) - (start) + 1, \ + .size = (end) - (start) + 1, \ } static const struct pinctrl_pin_desc southwest_pins[] = { @@ -288,40 +224,37 @@ static const unsigned southwest_i2c6_pins[] = { 47, 51 }; static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; -/* LPE I2S TXD pins need to have invert_oe set */ -static const struct chv_alternate_function southwest_lpe_altfuncs[] = { - ALTERNATE_FUNCTION(30, 1, true), - ALTERNATE_FUNCTION(34, 1, true), - ALTERNATE_FUNCTION(97, 1, true), +/* Some of LPE I2S TXD pins need to have OE inversion set */ +static const unsigned int southwest_lpe_altfuncs[] = { + PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ + PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ + PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ }; /* * Two spi3 chipselects are available in different mode than the main spi3 - * functionality, which is using mode 1. + * functionality, which is using mode 2. */ -static const struct chv_alternate_function southwest_spi3_altfuncs[] = { - ALTERNATE_FUNCTION(76, 3, false), - ALTERNATE_FUNCTION(80, 3, false), +static const unsigned int southwest_spi3_altfuncs[] = { + PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ + PINMODE(2, 0), /* 82 */ }; -static const struct chv_pingroup southwest_groups[] = { - PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false), - PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false), - PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false), - PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false), - PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), - - PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, - southwest_lpe_altfuncs), - PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, - southwest_spi3_altfuncs), +static const struct intel_pingroup southwest_groups[] = { + PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), + PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), + PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), + PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), + PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), + PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), + PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), + PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), + PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), + PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), + PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), + PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), + PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), + PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), }; static const char * const southwest_uart0_groups[] = { "uart0_grp" }; @@ -360,14 +293,14 @@ static const struct intel_function southwest_functions[] = { FUNCTION("spi3", southwest_spi3_groups), }; -static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { - GPIO_PINRANGE(0, 7), - GPIO_PINRANGE(15, 22), - GPIO_PINRANGE(30, 37), - GPIO_PINRANGE(45, 52), - GPIO_PINRANGE(60, 67), - GPIO_PINRANGE(75, 82), - GPIO_PINRANGE(90, 97), +static const struct intel_padgroup southwest_gpps[] = { + CHV_GPP(0, 7), + CHV_GPP(15, 22), + CHV_GPP(30, 37), + CHV_GPP(45, 52), + CHV_GPP(60, 67), + CHV_GPP(75, 82), + CHV_GPP(90, 97), }; static const struct chv_community southwest_community = { @@ -378,8 +311,8 @@ static const struct chv_community southwest_community = { .ngroups = ARRAY_SIZE(southwest_groups), .functions = southwest_functions, .nfunctions = ARRAY_SIZE(southwest_functions), - .gpio_ranges = southwest_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), + .gpps = southwest_gpps, + .ngpps = ARRAY_SIZE(southwest_gpps), /* * Southwest community can generate GPIO interrupts only for the * first 8 interrupts. The upper half (8-15) can only be used to @@ -455,20 +388,20 @@ static const struct pinctrl_pin_desc north_pins[] = { PINCTRL_PIN(72, "PANEL0_VDDEN"), }; -static const struct chv_gpio_pinrange north_gpio_ranges[] = { - GPIO_PINRANGE(0, 8), - GPIO_PINRANGE(15, 27), - GPIO_PINRANGE(30, 41), - GPIO_PINRANGE(45, 56), - GPIO_PINRANGE(60, 72), +static const struct intel_padgroup north_gpps[] = { + CHV_GPP(0, 8), + CHV_GPP(15, 27), + CHV_GPP(30, 41), + CHV_GPP(45, 56), + CHV_GPP(60, 72), }; static const struct chv_community north_community = { .uid = "2", .pins = north_pins, .npins = ARRAY_SIZE(north_pins), - .gpio_ranges = north_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), + .gpps = north_gpps, + .ngpps = ARRAY_SIZE(north_gpps), /* * North community can generate GPIO interrupts only for the first * 8 interrupts. The upper half (8-15) can only be used to trigger @@ -506,17 +439,17 @@ static const struct pinctrl_pin_desc east_pins[] = { PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), }; -static const struct chv_gpio_pinrange east_gpio_ranges[] = { - GPIO_PINRANGE(0, 11), - GPIO_PINRANGE(15, 26), +static const struct intel_padgroup east_gpps[] = { + CHV_GPP(0, 11), + CHV_GPP(15, 26), }; static const struct chv_community east_community = { .uid = "3", .pins = east_pins, .npins = ARRAY_SIZE(east_pins), - .gpio_ranges = east_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), + .gpps = east_gpps, + .ngpps = ARRAY_SIZE(east_gpps), .nirqs = 16, .acpi_space_id = 0x93, }; @@ -596,14 +529,14 @@ static const unsigned southeast_sdmmc3_pins[] = { static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; -static const struct chv_pingroup southeast_groups[] = { - PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false), - PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), - PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false), - PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false), +static const struct intel_pingroup southeast_groups[] = { + PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), + PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), + PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), + PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), }; static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; @@ -624,13 +557,13 @@ static const struct intel_function southeast_functions[] = { FUNCTION("spi2", southeast_spi2_groups), }; -static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { - GPIO_PINRANGE(0, 7), - GPIO_PINRANGE(15, 26), - GPIO_PINRANGE(30, 35), - GPIO_PINRANGE(45, 52), - GPIO_PINRANGE(60, 69), - GPIO_PINRANGE(75, 85), +static const struct intel_padgroup southeast_gpps[] = { + CHV_GPP(0, 7), + CHV_GPP(15, 26), + CHV_GPP(30, 35), + CHV_GPP(45, 52), + CHV_GPP(60, 69), + CHV_GPP(75, 85), }; static const struct chv_community southeast_community = { @@ -641,8 +574,8 @@ static const struct chv_community southeast_community = { .ngroups = ARRAY_SIZE(southeast_groups), .functions = southeast_functions, .nfunctions = ARRAY_SIZE(southeast_functions), - .gpio_ranges = southeast_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), + .gpps = southeast_gpps, + .ngpps = ARRAY_SIZE(southeast_gpps), .nirqs = 16, .acpi_space_id = 0x94, }; @@ -789,7 +722,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct chv_pingroup *grp; + const struct intel_pingroup *grp; unsigned long flags; int i; @@ -808,22 +741,21 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, } for (i = 0; i < grp->npins; i++) { - const struct chv_alternate_function *altfunc = &grp->altfunc; int pin = grp->pins[i]; void __iomem *reg; + unsigned int mode; + bool invert_oe; u32 value; /* Check if there is pin-specific config */ - if (grp->overrides) { - int j; - - for (j = 0; j < grp->noverrides; j++) { - if (grp->overrides[j].pin == pin) { - altfunc = &grp->overrides[j]; - break; - } - } - } + if (grp->modes) + mode = grp->modes[i]; + else + mode = grp->mode; + + /* Extract OE inversion */ + invert_oe = mode & PINMODE_INVERT_OE; + mode &= ~PINMODE_INVERT_OE; reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); value = readl(reg); @@ -831,18 +763,18 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, value &= ~CHV_PADCTRL0_GPIOEN; /* Set to desired mode */ value &= ~CHV_PADCTRL0_PMODE_MASK; - value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; + value |= mode << CHV_PADCTRL0_PMODE_SHIFT; chv_writel(value, reg); /* Update for invert_oe */ reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; - if (altfunc->invert_oe) + if (invert_oe) value |= CHV_PADCTRL1_INVRXTX_TXENABLE; chv_writel(value, reg); dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", - pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); + pin, mode, invert_oe ? "" : "not "); } raw_spin_unlock_irqrestore(&chv_lock, flags); @@ -1479,11 +1411,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) struct chv_pinctrl *pctrl = gpiochip_get_data(gc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; + unsigned long flags; u32 intr_line; chained_irq_enter(chip, desc); + raw_spin_lock_irqsave(&chv_lock, flags); pending = readl(pctrl->regs + CHV_INTSTAT); + raw_spin_unlock_irqrestore(&chv_lock, flags); + for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { unsigned int irq, offset; @@ -1590,14 +1526,14 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) { struct chv_pinctrl *pctrl = gpiochip_get_data(chip); const struct chv_community *community = pctrl->community; - const struct chv_gpio_pinrange *range; + const struct intel_padgroup *gpp; int ret, i; - for (i = 0; i < community->ngpio_ranges; i++) { - range = &community->gpio_ranges[i]; + for (i = 0; i < community->ngpps; i++) { + gpp = &community->gpps[i]; ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), - range->base, range->base, - range->npins); + gpp->base, gpp->base, + gpp->size); if (ret) { dev_err(pctrl->dev, "failed to add GPIO pin range\n"); return ret; @@ -1609,7 +1545,7 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) { - const struct chv_gpio_pinrange *range; + const struct intel_padgroup *gpp; struct gpio_chip *chip = &pctrl->chip; bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); const struct chv_community *community = pctrl->community; @@ -1657,12 +1593,12 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } if (!need_valid_mask) { - for (i = 0; i < community->ngpio_ranges; i++) { - range = &community->gpio_ranges[i]; + for (i = 0; i < community->ngpps; i++) { + gpp = &community->gpps[i]; irq_domain_associate_many(chip->irq.domain, irq_base, - range->base, range->npins); - irq_base += range->npins; + gpp->base, gpp->size); + irq_base += gpp->size; } } diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 6489e9bbb61f..429b5a83acf0 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -29,8 +29,6 @@ .gpio_base = (g), \ } -#define ICL_NO_GPIO -1 - #define ICL_COMMUNITY(b, s, e, g) \ { \ .barno = (b), \ @@ -305,29 +303,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = { }; static const struct intel_padgroup icllp_community0_gpps[] = { - ICL_GPP(0, 0, 7, 0), /* GPP_G */ - ICL_GPP(1, 8, 33, 32), /* GPP_B */ - ICL_GPP(2, 34, 58, 64), /* GPP_A */ + ICL_GPP(0, 0, 7, 0), /* GPP_G */ + ICL_GPP(1, 8, 33, 32), /* GPP_B */ + ICL_GPP(2, 34, 58, 64), /* GPP_A */ }; static const struct intel_padgroup icllp_community1_gpps[] = { - ICL_GPP(0, 59, 82, 96), /* GPP_H */ - ICL_GPP(1, 83, 103, 128), /* GPP_D */ - ICL_GPP(2, 104, 123, 160), /* GPP_F */ - ICL_GPP(3, 124, 152, 192), /* vGPIO */ + ICL_GPP(0, 59, 82, 96), /* GPP_H */ + ICL_GPP(1, 83, 103, 128), /* GPP_D */ + ICL_GPP(2, 104, 123, 160), /* GPP_F */ + ICL_GPP(3, 124, 152, 192), /* vGPIO */ }; static const struct intel_padgroup icllp_community4_gpps[] = { - ICL_GPP(0, 153, 176, 224), /* GPP_C */ - ICL_GPP(1, 177, 182, ICL_NO_GPIO), /* HVCMOS */ - ICL_GPP(2, 183, 206, 256), /* GPP_E */ - ICL_GPP(3, 207, 215, ICL_NO_GPIO), /* JTAG */ + ICL_GPP(0, 153, 176, 224), /* GPP_C */ + ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ICL_GPP(2, 183, 206, 256), /* GPP_E */ + ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup icllp_community5_gpps[] = { - ICL_GPP(0, 216, 223, 288), /* GPP_R */ - ICL_GPP(1, 224, 231, 320), /* GPP_S */ - ICL_GPP(2, 232, 240, ICL_NO_GPIO), /* SPI */ + ICL_GPP(0, 216, 223, 288), /* GPP_R */ + ICL_GPP(1, 224, 231, 320), /* GPP_S */ + ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community icllp_communities[] = { diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 74fdfd2b9ff5..6a274e20d926 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -798,7 +798,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, for (j = 0; j < comm->ngpps; j++) { const struct intel_padgroup *pgrp = &comm->gpps[j]; - if (pgrp->gpio_base < 0) + if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; if (offset >= pgrp->gpio_base && @@ -1138,7 +1138,7 @@ static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, for (i = 0; i < community->ngpps; i++) { const struct intel_padgroup *gpp = &community->gpps[i]; - if (gpp->gpio_base < 0) + if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), @@ -1180,7 +1180,7 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) for (j = 0; j < community->ngpps; j++) { const struct intel_padgroup *gpp = &community->gpps[j]; - if (gpp->gpio_base < 0) + if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; if (gpp->gpio_base + gpp->size > ngpio) @@ -1276,8 +1276,18 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, if (gpps[i].size > 32) return -EINVAL; - if (!gpps[i].gpio_base) - gpps[i].gpio_base = gpps[i].base; + /* Special treatment for GPIO base */ + switch (gpps[i].gpio_base) { + case INTEL_GPIO_BASE_MATCH: + gpps[i].gpio_base = gpps[i].base; + break; + case INTEL_GPIO_BASE_ZERO: + gpps[i].gpio_base = 0; + break; + case INTEL_GPIO_BASE_NOMAP: + default: + break; + } gpps[i].padown_num = padown_num; @@ -1596,7 +1606,7 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, struct device *dev = pctrl->dev; u32 requested; - if (padgrp->gpio_base < 0) + if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) return; requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index c6f066f6d3fb..cc78c483518f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -53,8 +53,7 @@ struct intel_function { * @reg_num: GPI_IS register number * @base: Starting pin of this group * @size: Size of this group (maximum is 32). - * @gpio_base: Starting GPIO base of this group (%0 if matches with @base, - * and %-1 if no GPIO mapping should be created) + * @gpio_base: Starting GPIO base of this group * @padown_num: PAD_OWN register number (assigned by the core driver) * * If pad groups of a community are not the same size, use this structure @@ -69,6 +68,19 @@ struct intel_padgroup { }; /** + * enum - Special treatment for GPIO base in pad group + * + * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0 + * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created + * @INTEL_GPIO_BASE_MATCH: matches with starting pin number + */ +enum { + INTEL_GPIO_BASE_ZERO = -2, + INTEL_GPIO_BASE_NOMAP = -1, + INTEL_GPIO_BASE_MATCH = 0, +}; + +/** * struct intel_community - Intel pin community description * @barno: MMIO BAR number where registers for this community reside * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 @@ -82,20 +94,20 @@ struct intel_padgroup { * @ie_offset: Register offset of GPI_IE from @regs. * @features: Additional features supported by the hardware * @pin_base: Starting pin of pins in this community + * @npins: Number of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, - * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. + * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. * @gpp_num_padown_regs: Number of pad registers each pad group consumes at * minimum. Use %0 if the number of registers can be * determined by the size of the group. - * @npins: Number of pins in this community * @gpps: Pad groups if the controller has variable size pad groups * @ngpps: Number of pad groups in this community * @pad_map: Optional non-linear mapping of the pads * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * - * Most Intel GPIO host controllers this driver supports each pad group is - * of equal size (except the last one). In that case the driver can just + * In some of Intel GPIO host controllers this driver supports each pad group + * is of equal size (except the last one). In that case the driver can just * fill in @gpp_size field and let the core driver to handle the rest. If * the controller has pad groups of variable size the client driver can * pass custom @gpps and @ngpps instead. @@ -109,12 +121,13 @@ struct intel_community { unsigned int ie_offset; unsigned int features; unsigned int pin_base; + size_t npins; unsigned int gpp_size; unsigned int gpp_num_padown_regs; - size_t npins; const struct intel_padgroup *gpps; size_t ngpps; const unsigned int *pad_map; + /* Reserved for the core driver */ void __iomem *regs; void __iomem *pad_regs; diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c new file mode 100644 index 000000000000..9bd0e8e6310c --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Jasper Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + */ + +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define JSL_PAD_OWN 0x020 +#define JSL_PADCFGLOCK 0x080 +#define JSL_HOSTSW_OWN 0x0b0 +#define JSL_GPI_IS 0x100 +#define JSL_GPI_IE 0x120 + +#define JSL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define JSL_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = JSL_PAD_OWN, \ + .padcfglock_offset = JSL_PADCFGLOCK, \ + .hostown_offset = JSL_HOSTSW_OWN, \ + .is_offset = JSL_GPI_IS, \ + .ie_offset = JSL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Jasper Lake */ +static const struct pinctrl_pin_desc jsl_pins[] = { + /* GPP_F */ + PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"), + PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"), + PINCTRL_PIN(2, "EMMC_HIP_MON"), + PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"), + PINCTRL_PIN(4, "CNV_RF_RESET_B"), + PINCTRL_PIN(5, "MODEM_CLKREQ"), + PINCTRL_PIN(6, "CNV_PA_BLANKING"), + PINCTRL_PIN(7, "EMMC_CMD"), + PINCTRL_PIN(8, "EMMC_DATA0"), + PINCTRL_PIN(9, "EMMC_DATA1"), + PINCTRL_PIN(10, "EMMC_DATA2"), + PINCTRL_PIN(11, "EMMC_DATA3"), + PINCTRL_PIN(12, "EMMC_DATA4"), + PINCTRL_PIN(13, "EMMC_DATA5"), + PINCTRL_PIN(14, "EMMC_DATA6"), + PINCTRL_PIN(15, "EMMC_DATA7"), + PINCTRL_PIN(16, "EMMC_RCLK"), + PINCTRL_PIN(17, "EMMC_CLK"), + PINCTRL_PIN(18, "EMMC_RESETB"), + PINCTRL_PIN(19, "A4WP_PRESENT"), + /* GPP_B */ + PINCTRL_PIN(20, "CORE_VID_0"), + PINCTRL_PIN(21, "CORE_VID_1"), + PINCTRL_PIN(22, "VRALERTB"), + PINCTRL_PIN(23, "CPU_GP_2"), + PINCTRL_PIN(24, "CPU_GP_3"), + PINCTRL_PIN(25, "SRCCLKREQB_0"), + PINCTRL_PIN(26, "SRCCLKREQB_1"), + PINCTRL_PIN(27, "SRCCLKREQB_2"), + PINCTRL_PIN(28, "SRCCLKREQB_3"), + PINCTRL_PIN(29, "SRCCLKREQB_4"), + PINCTRL_PIN(30, "SRCCLKREQB_5"), + PINCTRL_PIN(31, "PMCALERTB"), + PINCTRL_PIN(32, "SLP_S0B"), + PINCTRL_PIN(33, "PLTRSTB"), + PINCTRL_PIN(34, "SPKR"), + PINCTRL_PIN(35, "GSPI0_CS0B"), + PINCTRL_PIN(36, "GSPI0_CLK"), + PINCTRL_PIN(37, "GSPI0_MISO"), + PINCTRL_PIN(38, "GSPI0_MOSI"), + PINCTRL_PIN(39, "GSPI1_CS0B"), + PINCTRL_PIN(40, "GSPI1_CLK"), + PINCTRL_PIN(41, "GSPI1_MISO"), + PINCTRL_PIN(42, "GSPI1_MOSI"), + PINCTRL_PIN(43, "DDSP_HPD_A"), + PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(46, "ESPI_IO_0"), + PINCTRL_PIN(47, "ESPI_IO_1"), + PINCTRL_PIN(48, "ESPI_IO_2"), + PINCTRL_PIN(49, "ESPI_IO_3"), + PINCTRL_PIN(50, "ESPI_CSB"), + PINCTRL_PIN(51, "ESPI_CLK"), + PINCTRL_PIN(52, "ESPI_RESETB"), + PINCTRL_PIN(53, "SMBCLK"), + PINCTRL_PIN(54, "SMBDATA"), + PINCTRL_PIN(55, "SMBALERTB"), + PINCTRL_PIN(56, "CPU_GP_0"), + PINCTRL_PIN(57, "CPU_GP_1"), + PINCTRL_PIN(58, "USB2_OCB_1"), + PINCTRL_PIN(59, "USB2_OCB_2"), + PINCTRL_PIN(60, "USB2_OCB_3"), + PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"), + PINCTRL_PIN(62, "DDSP_HPD_B"), + PINCTRL_PIN(63, "DDSP_HPD_C"), + PINCTRL_PIN(64, "USB2_OCB_0"), + PINCTRL_PIN(65, "PCHHOTB"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(67, "SNDW1_CLK"), + PINCTRL_PIN(68, "SNDW1_DATA"), + PINCTRL_PIN(69, "SNDW2_CLK"), + PINCTRL_PIN(70, "SNDW2_DATA"), + PINCTRL_PIN(71, "SNDW1_CLK"), + PINCTRL_PIN(72, "SNDW1_DATA"), + PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"), + PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"), + /* GPP_R */ + PINCTRL_PIN(75, "HDA_BCLK"), + PINCTRL_PIN(76, "HDA_SYNC"), + PINCTRL_PIN(77, "HDA_SDO"), + PINCTRL_PIN(78, "HDA_SDI_0"), + PINCTRL_PIN(79, "HDA_RSTB"), + PINCTRL_PIN(80, "HDA_SDI_1"), + PINCTRL_PIN(81, "I2S1_SFRM"), + PINCTRL_PIN(82, "I2S1_TXD"), + /* GPP_H */ + PINCTRL_PIN(83, "GPPC_H_0"), + PINCTRL_PIN(84, "SD_PWR_EN_B"), + PINCTRL_PIN(85, "MODEM_CLKREQ"), + PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(87, "I2C2_SDA"), + PINCTRL_PIN(88, "I2C2_SCL"), + PINCTRL_PIN(89, "I2C3_SDA"), + PINCTRL_PIN(90, "I2C3_SCL"), + PINCTRL_PIN(91, "I2C4_SDA"), + PINCTRL_PIN(92, "I2C4_SCL"), + PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(94, "I2S2_SCLK"), + PINCTRL_PIN(95, "I2S2_SFRM"), + PINCTRL_PIN(96, "I2S2_TXD"), + PINCTRL_PIN(97, "I2S2_RXD"), + PINCTRL_PIN(98, "I2S1_SCLK"), + PINCTRL_PIN(99, "GPPC_H_16"), + PINCTRL_PIN(100, "GPPC_H_17"), + PINCTRL_PIN(101, "GPPC_H_18"), + PINCTRL_PIN(102, "GPPC_H_19"), + PINCTRL_PIN(103, "GPPC_H_20"), + PINCTRL_PIN(104, "GPPC_H_21"), + PINCTRL_PIN(105, "GPPC_H_22"), + PINCTRL_PIN(106, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(107, "SPI1_CSB"), + PINCTRL_PIN(108, "SPI1_CLK"), + PINCTRL_PIN(109, "SPI1_MISO_IO_1"), + PINCTRL_PIN(110, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(111, "ISH_I2C0_SDA"), + PINCTRL_PIN(112, "ISH_I2C0_SCL"), + PINCTRL_PIN(113, "ISH_I2C1_SDA"), + PINCTRL_PIN(114, "ISH_I2C1_SCL"), + PINCTRL_PIN(115, "ISH_SPI_CSB"), + PINCTRL_PIN(116, "ISH_SPI_CLK"), + PINCTRL_PIN(117, "ISH_SPI_MISO"), + PINCTRL_PIN(118, "ISH_SPI_MOSI"), + PINCTRL_PIN(119, "ISH_UART0_RXD"), + PINCTRL_PIN(120, "ISH_UART0_TXD"), + PINCTRL_PIN(121, "ISH_UART0_RTSB"), + PINCTRL_PIN(122, "ISH_UART0_CTSB"), + PINCTRL_PIN(123, "SPI1_IO_2"), + PINCTRL_PIN(124, "SPI1_IO_3"), + PINCTRL_PIN(125, "I2S_MCLK"), + PINCTRL_PIN(126, "CNV_MFUART2_RXD"), + PINCTRL_PIN(127, "CNV_MFUART2_TXD"), + PINCTRL_PIN(128, "CNV_PA_BLANKING"), + PINCTRL_PIN(129, "I2C5_SDA"), + PINCTRL_PIN(130, "I2C5_SCL"), + PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(133, "CNV_BTEN"), + PINCTRL_PIN(134, "CNV_WCEN"), + PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(136, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(137, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(138, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(141, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(142, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(145, "vUART0_TXD"), + PINCTRL_PIN(146, "vUART0_RXD"), + PINCTRL_PIN(147, "vUART0_CTS_B"), + PINCTRL_PIN(148, "vUART0_RTS_B"), + PINCTRL_PIN(149, "vISH_UART0_TXD"), + PINCTRL_PIN(150, "vISH_UART0_RXD"), + PINCTRL_PIN(151, "vISH_UART0_CTS_B"), + PINCTRL_PIN(152, "vISH_UART0_RTS_B"), + PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(157, "vI2S2_SCLK"), + PINCTRL_PIN(158, "vI2S2_SFRM"), + PINCTRL_PIN(159, "vI2S2_TXD"), + PINCTRL_PIN(160, "vI2S2_RXD"), + PINCTRL_PIN(161, "vSD3_CD_B"), + /* GPP_C */ + PINCTRL_PIN(162, "GPPC_C_0"), + PINCTRL_PIN(163, "GPPC_C_1"), + PINCTRL_PIN(164, "GPPC_C_2"), + PINCTRL_PIN(165, "GPPC_C_3"), + PINCTRL_PIN(166, "GPPC_C_4"), + PINCTRL_PIN(167, "GPPC_C_5"), + PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(169, "SUSACKB"), + PINCTRL_PIN(170, "UART0_RXD"), + PINCTRL_PIN(171, "UART0_TXD"), + PINCTRL_PIN(172, "UART0_RTSB"), + PINCTRL_PIN(173, "UART0_CTSB"), + PINCTRL_PIN(174, "UART1_RXD"), + PINCTRL_PIN(175, "UART1_TXD"), + PINCTRL_PIN(176, "UART1_RTSB"), + PINCTRL_PIN(177, "UART1_CTSB"), + PINCTRL_PIN(178, "I2C0_SDA"), + PINCTRL_PIN(179, "I2C0_SCL"), + PINCTRL_PIN(180, "I2C1_SDA"), + PINCTRL_PIN(181, "I2C1_SCL"), + PINCTRL_PIN(182, "UART2_RXD"), + PINCTRL_PIN(183, "UART2_TXD"), + PINCTRL_PIN(184, "UART2_RTSB"), + PINCTRL_PIN(185, "UART2_CTSB"), + /* HVCMOS */ + PINCTRL_PIN(186, "L_BKLTEN"), + PINCTRL_PIN(187, "L_BKLTCTL"), + PINCTRL_PIN(188, "L_VDDEN"), + PINCTRL_PIN(189, "SYS_PWROK"), + PINCTRL_PIN(190, "SYS_RESETB"), + PINCTRL_PIN(191, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(192, "ISH_GP_0"), + PINCTRL_PIN(193, "ISH_GP_1"), + PINCTRL_PIN(194, "IMGCLKOUT_1"), + PINCTRL_PIN(195, "ISH_GP_2"), + PINCTRL_PIN(196, "IMGCLKOUT_2"), + PINCTRL_PIN(197, "SATA_LEDB"), + PINCTRL_PIN(198, "IMGCLKOUT_3"), + PINCTRL_PIN(199, "ISH_GP_3"), + PINCTRL_PIN(200, "ISH_GP_4"), + PINCTRL_PIN(201, "ISH_GP_5"), + PINCTRL_PIN(202, "ISH_GP_6"), + PINCTRL_PIN(203, "ISH_GP_7"), + PINCTRL_PIN(204, "IMGCLKOUT_4"), + PINCTRL_PIN(205, "DDPA_CTRLCLK"), + PINCTRL_PIN(206, "DDPA_CTRLDATA"), + PINCTRL_PIN(207, "DDPB_CTRLCLK"), + PINCTRL_PIN(208, "DDPB_CTRLDATA"), + PINCTRL_PIN(209, "DDPC_CTRLCLK"), + PINCTRL_PIN(210, "DDPC_CTRLDATA"), + PINCTRL_PIN(211, "IMGCLKOUT_5"), + PINCTRL_PIN(212, "CNV_BRI_DT"), + PINCTRL_PIN(213, "CNV_BRI_RSP"), + PINCTRL_PIN(214, "CNV_RGI_DT"), + PINCTRL_PIN(215, "CNV_RGI_RSP"), + /* GPP_G */ + PINCTRL_PIN(216, "SD3_CMD"), + PINCTRL_PIN(217, "SD3_D0"), + PINCTRL_PIN(218, "SD3_D1"), + PINCTRL_PIN(219, "SD3_D2"), + PINCTRL_PIN(220, "SD3_D3"), + PINCTRL_PIN(221, "SD3_CDB"), + PINCTRL_PIN(222, "SD3_CLK"), + PINCTRL_PIN(223, "SD3_WP"), +}; + +static const struct intel_padgroup jsl_community0_gpps[] = { + JSL_GPP(0, 0, 19, 320), /* GPP_F */ + JSL_GPP(1, 20, 45, 32), /* GPP_B */ + JSL_GPP(2, 46, 66, 64), /* GPP_A */ + JSL_GPP(3, 67, 74, 96), /* GPP_S */ + JSL_GPP(4, 75, 82, 128), /* GPP_R */ +}; + +static const struct intel_padgroup jsl_community1_gpps[] = { + JSL_GPP(0, 83, 106, 160), /* GPP_H */ + JSL_GPP(1, 107, 132, 192), /* GPP_D */ + JSL_GPP(2, 133, 161, 224), /* vGPIO */ + JSL_GPP(3, 162, 185, 256), /* GPP_C */ +}; + +static const struct intel_padgroup jsl_community4_gpps[] = { + JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + JSL_GPP(1, 192, 215, 288), /* GPP_E */ +}; + +static const struct intel_padgroup jsl_community5_gpps[] = { + JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */ +}; + +static const struct intel_community jsl_communities[] = { + JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps), + JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps), + JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps), + JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data jsl_soc_data = { + .pins = jsl_pins, + .npins = ARRAY_SIZE(jsl_pins), + .communities = jsl_communities, + .ncommunities = ARRAY_SIZE(jsl_communities), +}; + +static const struct acpi_device_id jsl_pinctrl_acpi_match[] = { + { "INT34C8", (kernel_ulong_t)&jsl_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops); + +static struct platform_driver jsl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "jasperlake-pinctrl", + .acpi_match_table = jsl_pinctrl_acpi_match, + .pm = &jsl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(jsl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index e928742c7181..a45b8f2182fd 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -794,11 +794,11 @@ static int lp_gpio_probe(struct platform_device *pdev) const struct intel_pinctrl_soc_data *soc; struct intel_pinctrl *lg; struct gpio_chip *gc; - struct resource *io_rc, *irq_rc; struct device *dev = &pdev->dev; + struct resource *io_rc; void __iomem *regs; unsigned int i; - int ret; + int irq, ret; soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); if (!soc) @@ -870,8 +870,8 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->parent = dev; /* set up interrupts */ - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq_rc && irq_rc->start) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { struct gpio_irq_chip *girq; girq = &gc->irq; @@ -884,7 +884,7 @@ static int lp_gpio_probe(struct platform_device *pdev) GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned int)irq_rc->start; + girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 330c8f077b73..4d7a86a5a37b 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -15,17 +15,18 @@ #include "pinctrl-intel.h" -#define SPT_PAD_OWN 0x020 -#define SPT_PADCFGLOCK 0x0a0 -#define SPT_HOSTSW_OWN 0x0d0 -#define SPT_GPI_IS 0x100 -#define SPT_GPI_IE 0x120 +#define SPT_PAD_OWN 0x020 +#define SPT_H_PADCFGLOCK 0x090 +#define SPT_LP_PADCFGLOCK 0x0a0 +#define SPT_HOSTSW_OWN 0x0d0 +#define SPT_GPI_IS 0x100 +#define SPT_GPI_IE 0x120 #define SPT_COMMUNITY(b, s, e) \ { \ .barno = (b), \ .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_PADCFGLOCK, \ + .padcfglock_offset = SPT_LP_PADCFGLOCK, \ .hostown_offset = SPT_HOSTSW_OWN, \ .is_offset = SPT_GPI_IS, \ .ie_offset = SPT_GPI_IE, \ @@ -47,7 +48,7 @@ { \ .barno = (b), \ .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_PADCFGLOCK, \ + .padcfglock_offset = SPT_H_PADCFGLOCK, \ .hostown_offset = SPT_HOSTSW_OWN, \ .is_offset = SPT_GPI_IS, \ .ie_offset = SPT_GPI_IE, \ diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 08a86f6fdea6..bcfd7548e282 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -21,8 +21,6 @@ #define TGL_GPI_IS 0x100 #define TGL_GPI_IE 0x120 -#define TGL_NO_GPIO -1 - #define TGL_GPP(r, s, e, g) \ { \ .reg_num = (r), \ @@ -342,30 +340,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = { }; static const struct intel_padgroup tgllp_community0_gpps[] = { - TGL_GPP(0, 0, 25, 0), /* GPP_B */ - TGL_GPP(1, 26, 41, 32), /* GPP_T */ - TGL_GPP(2, 42, 66, 64), /* GPP_A */ + TGL_GPP(0, 0, 25, 0), /* GPP_B */ + TGL_GPP(1, 26, 41, 32), /* GPP_T */ + TGL_GPP(2, 42, 66, 64), /* GPP_A */ }; static const struct intel_padgroup tgllp_community1_gpps[] = { - TGL_GPP(0, 67, 74, 96), /* GPP_S */ - TGL_GPP(1, 75, 98, 128), /* GPP_H */ - TGL_GPP(2, 99, 119, 160), /* GPP_D */ - TGL_GPP(3, 120, 143, 192), /* GPP_U */ - TGL_GPP(4, 144, 170, 224), /* vGPIO */ + TGL_GPP(0, 67, 74, 96), /* GPP_S */ + TGL_GPP(1, 75, 98, 128), /* GPP_H */ + TGL_GPP(2, 99, 119, 160), /* GPP_D */ + TGL_GPP(3, 120, 143, 192), /* GPP_U */ + TGL_GPP(4, 144, 170, 224), /* vGPIO */ }; static const struct intel_padgroup tgllp_community4_gpps[] = { - TGL_GPP(0, 171, 194, 256), /* GPP_C */ - TGL_GPP(1, 195, 219, 288), /* GPP_F */ - TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */ - TGL_GPP(3, 226, 250, 320), /* GPP_E */ - TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */ + TGL_GPP(0, 171, 194, 256), /* GPP_C */ + TGL_GPP(1, 195, 219, 288), /* GPP_F */ + TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + TGL_GPP(3, 226, 250, 320), /* GPP_E */ + TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup tgllp_community5_gpps[] = { - TGL_GPP(0, 260, 267, 352), /* GPP_R */ - TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */ + TGL_GPP(0, 260, 267, 352), /* GPP_R */ + TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community tgllp_communities[] = { |