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author | 2018-12-26 22:45:06 +0100 | |
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committer | 2019-01-07 18:12:24 +0000 | |
commit | aa54c1c9d90e6db75190813907190fadcce1bf45 (patch) | |
tree | 266ca5b618c19d75c10e00d1198942cc8e3f081e /drivers/spi/spi-fsl-dspi.c | |
parent | spi: lpspi: Fix CLK pin becomes low before one transfer (diff) | |
download | linux-aa54c1c9d90e6db75190813907190fadcce1bf45.tar.gz linux-aa54c1c9d90e6db75190813907190fadcce1bf45.tar.bz2 linux-aa54c1c9d90e6db75190813907190fadcce1bf45.zip |
spi: fix initial SPI_SR value in spi-fsl-dspi
On ColdFire mcf54418, using DSPI_DMA_MODE mode, spi transfers
at first boot stage are not succeding:
m25p80 spi0.1: unrecognized JEDEC id bytes: 00, 00, 00
The reason is the SPI_SR initial value set by the driver, that
is not clearing (not setting to 1) the RF_DF flag. After a tour
on the dspi hw modules that use this driver(Vybrid, ColdFire and
ls1021a) a better init value for SR register has been set.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-fsl-dspi.c')
-rw-r--r-- | drivers/spi/spi-fsl-dspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 5e10dc5c93a5..7b605f95dbef 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -67,7 +67,7 @@ #define SPI_SR 0x2c #define SPI_SR_EOQF 0x10000000 #define SPI_SR_TCFQF 0x80000000 -#define SPI_SR_CLEAR 0xdaad0000 +#define SPI_SR_CLEAR 0x9aaf0000 #define SPI_RSER_TFFFE BIT(25) #define SPI_RSER_TFFFD BIT(24) |