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| author |  Conor Dooley <conor.dooley@microchip.com>
| 2024-05-08 16:46:51 +0100 |
|---|---|---|
| committer |  Mark Brown <broonie@kernel.org>
| 2024-05-09 06:59:19 +0200 |
| commit | ef13561d2b163ac0ae6befa53bca58a26dc3320b (patch) | |
| tree | 3c5b547fea271f8eb307b12b926681cc4653fcd6 /drivers/spi | |
| parent | spi: stm32: enable controller before asserting CS (diff) | |
| download | linux-ef13561d2b163ac0ae6befa53bca58a26dc3320b.tar.gz linux-ef13561d2b163ac0ae6befa53bca58a26dc3320b.tar.bz2 linux-ef13561d2b163ac0ae6befa53bca58a26dc3320b.zip | |
spi: microchip-core-qspi: fix setting spi bus clock rate
Before ORing the new clock rate with the control register value read
from the hardware, the existing clock rate needs to be masked off as
otherwise the existing value will interfere with the new one.
CC: stable@vger.kernel.org
Fixes: 8596124c4c1b ("spi: microchip-core-qspi: Add support for microchip fpga qspi controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240508-fox-unpiloted-b97e1535627b@spud
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-microchip-core-qspi.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c index 03d125a71fd9..09f16471c537 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -283,6 +283,7 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_devi } control = readl_relaxed(qspi->regs + REG_CONTROL); + control &= ~CONTROL_CLKRATE_MASK; control |= baud_rate_val << CONTROL_CLKRATE_SHIFT; writel_relaxed(control, qspi->regs + REG_CONTROL); control = readl_relaxed(qspi->regs + REG_CONTROL); |