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| author |  Peter Griffin <peter.griffin@linaro.org>
| 2024-04-26 13:20:00 +0100 |
|---|---|---|
| committer |  Martin K. Petersen <martin.petersen@oracle.com>
| 2024-05-06 21:34:37 -0400 |
| commit | 449adb00d4f7870eb07adedd34e4a4b69036ec12 (patch) | |
| tree | 6e674e08e24d2b24096e9baf060af231cbd07804 /drivers/ufs | |
| parent | scsi: ufs: dt-bindings: exynos: Add gs101 compatible (diff) | |
| download | linux-449adb00d4f7870eb07adedd34e4a4b69036ec12.tar.gz linux-449adb00d4f7870eb07adedd34e4a4b69036ec12.tar.bz2 linux-449adb00d4f7870eb07adedd34e4a4b69036ec12.zip | |
scsi: ufs: exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option
This option is intended to be set on platforms whose ufspr registers are
only accessible via smc call (such as gs101).
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-3-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/ufs')
| -rw-r--r-- | drivers/ufs/host/ufs-exynos.c | 5 | ||||
| -rw-r--r-- | drivers/ufs/host/ufs-exynos.h | 1 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 734d40f99e31..0219a5806619 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -1186,7 +1186,10 @@ static int exynos_ufs_init(struct ufs_hba *hba) if (ret) goto out; exynos_ufs_specify_phy_time_attr(ufs); - exynos_ufs_config_smu(ufs); + if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE)) + exynos_ufs_config_smu(ufs); + + hba->host->dma_alignment = SZ_4K - 1; return 0; out: diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h index a4bd6646d7f1..0fc21b6bbfcd 100644 --- a/drivers/ufs/host/ufs-exynos.h +++ b/drivers/ufs/host/ufs-exynos.h @@ -221,6 +221,7 @@ struct exynos_ufs { #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3) #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4) #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5) +#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6) }; #define for_each_ufs_rx_lane(ufs, i) \ |