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| author |  Shengjiu Wang <shengjiu.wang@nxp.com>
| 2023-07-25 12:56:23 +0800 |
|---|---|---|
| committer |  Abel Vesa <abel.vesa@linaro.org>
| 2023-08-14 12:27:52 +0300 |
| commit | a70cd8cdf7492006b547f46cc365eed79d331323 (patch) | |
| tree | b99e6affca32de782bce8a5cc5eeb325567e3473 /include/dt-bindings | |
| parent | clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() (diff) | |
| download | linux-a70cd8cdf7492006b547f46cc365eed79d331323.tar.gz linux-a70cd8cdf7492006b547f46cc365eed79d331323.tar.bz2 linux-a70cd8cdf7492006b547f46cc365eed79d331323.zip | |
dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
Add the clock dt-binding file for Audio Clock Mux. which
is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL.
Add the clockid for clocks in header file.
The Audio Clock Mux is binded with all the audio IP and audio clocks
in the subsystem, so need to list the power domain of related clocks
and IPs. Each clock and IP has a power domain, so there are so many
power domains.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1690260984-25744-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/imx8-clock.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 2e60ce4d2622..2242ff54fc5e 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -164,4 +164,32 @@ #define IMX_ADMA_LPCG_CLK_END 45 +#define IMX_ADMA_ACM_AUD_CLK0_SEL 0 +#define IMX_ADMA_ACM_AUD_CLK1_SEL 1 +#define IMX_ADMA_ACM_MCLKOUT0_SEL 2 +#define IMX_ADMA_ACM_MCLKOUT1_SEL 3 +#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4 +#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5 +#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6 +#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7 +#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8 +#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9 +#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10 +#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11 +#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12 +#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13 +#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14 +#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15 +#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16 +#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17 +#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18 +#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19 +#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20 +#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21 +#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22 +#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23 +#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24 + +#define IMX_ADMA_ACM_CLK_END 25 + #endif /* __DT_BINDINGS_CLOCK_IMX_H */ |