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authorGravatar Alex Deucher <alexander.deucher@amd.com> 2019-11-27 15:55:35 -0500
committerGravatar Alex Deucher <alexander.deucher@amd.com> 2020-04-28 16:20:29 -0400
commit4baa8ff0690e464443594353d63c989f0ed9f831 (patch)
treea5d4a41cc7c7710c962f8ce3fbcf9ffdf4d07bb0 /include/uapi/drm
parentdrm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10 (diff)
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drm/amdgpu: move CS secure flag next the structs where it's used
So it's not mixed up with the CTX stuff. Reviewed-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/amdgpu_drm.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 34cd0bae06bc..bea72eb8c147 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -205,9 +205,6 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
-/* Flag the command submission as secure */
-#define AMDGPU_CS_FLAGS_SECURE (1 << 0)
-
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET 0
/* this the context caused it */
@@ -561,6 +558,9 @@ struct drm_amdgpu_cs_chunk {
__u64 chunk_data;
};
+/* Flag the command submission as secure */
+#define AMDGPU_CS_FLAGS_SECURE (1 << 0)
+
struct drm_amdgpu_cs_in {
/** Rendering context id */
__u32 ctx_id;