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| author |  Shengjiu Wang <shengjiu.wang@nxp.com>
| 2023-11-23 09:14:53 +0800 |
|---|---|---|
| committer |  Mark Brown <broonie@kernel.org>
| 2023-11-23 12:41:46 +0000 |
| commit | 347ecf29a68cc8958fbcbd26ef410d07fe9d82f4 (patch) | |
| tree | 6e7e38abb9d23beb43c2f35d332104519f735d0d /sound/soc/intel/boards | |
| parent | ASoC: SOF: mediatek: mt8186: Add Google Steelix topology compatible (diff) | |
| download | linux-347ecf29a68cc8958fbcbd26ef410d07fe9d82f4.tar.gz linux-347ecf29a68cc8958fbcbd26ef410d07fe9d82f4.tar.bz2 linux-347ecf29a68cc8958fbcbd26ef410d07fe9d82f4.zip | |
ASoC: fsl_xcvr: refine the requested phy clock frequency
As the input phy clock frequency will divided by 2 by default
on i.MX8MP with the implementation of clk-imx8mp-audiomix driver,
So the requested frequency need to be updated.
The relation of phy clock is:
sai_pll_ref_sel
sai_pll
sai_pll_bypass
sai_pll_out
sai_pll_out_div2
earc_phy_cg
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Link: https://lore.kernel.org/r/1700702093-8008-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/boards')
0 files changed, 0 insertions, 0 deletions