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| author |  Ravi Bangoria <ravi.bangoria@amd.com>
| 2023-04-07 16:54:59 +0530 |
|---|---|---|
| committer |  Arnaldo Carvalho de Melo <acme@redhat.com>
| 2023-04-10 19:29:52 -0300 |
| commit | 3d3a3a49e20f006fa88e4fec5ad236864faa3a35 (patch) | |
| tree | 7f4ab2cd5bd1feffd39c94edff28ee8c3d057098 /tools/perf/util/amd-sample-raw.c | |
| parent | perf mem: Increase HISTC_MEM_LVL column size to 39 chars (diff) | |
| download | linux-3d3a3a49e20f006fa88e4fec5ad236864faa3a35.tar.gz linux-3d3a3a49e20f006fa88e4fec5ad236864faa3a35.tar.bz2 linux-3d3a3a49e20f006fa88e4fec5ad236864faa3a35.zip | |
perf script ibs: Change bit description according to latest AMD PPR ("Processor Programming Reference")
Some of the IBS_OP_DATA2 bit descriptions were stale (taken from old
version of PPR). Change it according to latest PPR.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Santosh Shukla <santosh.shukla@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/util/amd-sample-raw.c')
| -rw-r--r-- | tools/perf/util/amd-sample-raw.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tools/perf/util/amd-sample-raw.c b/tools/perf/util/amd-sample-raw.c index b0e70ce9d87a..6a6ddba76c75 100644 --- a/tools/perf/util/amd-sample-raw.c +++ b/tools/perf/util/amd-sample-raw.c @@ -105,17 +105,17 @@ static void pr_ibs_op_data2_extended(union ibs_op_data2 reg) static const char * const data_src_str[] = { "", " DataSrc 1=Local L3 or other L1/L2 in CCX", - " DataSrc 2=A peer cache in a near CCX", - " DataSrc 3=Data returned from DRAM", + " DataSrc 2=Another CCX cache in the same NUMA node", + " DataSrc 3=DRAM", " DataSrc 4=(reserved)", - " DataSrc 5=A peer cache in a far CCX", - " DataSrc 6=DRAM address map with \"long latency\" bit set", - " DataSrc 7=Data returned from MMIO/Config/PCI/APIC", - " DataSrc 8=Extension Memory (S-Link, GenZ, etc)", + " DataSrc 5=Another CCX cache in a different NUMA node", + " DataSrc 6=Long-latency DIMM", + " DataSrc 7=MMIO/Config/PCI/APIC", + " DataSrc 8=Extension Memory", " DataSrc 9=(reserved)", " DataSrc 10=(reserved)", " DataSrc 11=(reserved)", - " DataSrc 12=Peer Agent Memory", + " DataSrc 12=Coherent Memory of a different processor type", /* 13 to 31 are reserved. Avoid printing them. */ }; int data_src = (reg.data_src_hi << 3) | reg.data_src_lo; |