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| author |  Dan Williams <dan.j.williams@intel.com>
| 2022-05-18 16:35:00 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com>
| 2022-05-19 08:50:41 -0700 |
| commit | a12562bb70776093b270f79a4b6ef18f4bcead2b (patch) | |
| tree | c1a376497302c826d74bbda4d96d617270161928 /tools/testing/cxl/Kbuild | |
| parent | cxl/mem: Skip range enumeration if mem_enable clear (diff) | |
| download | linux-a12562bb70776093b270f79a4b6ef18f4bcead2b.tar.gz linux-a12562bb70776093b270f79a4b6ef18f4bcead2b.tar.bz2 linux-a12562bb70776093b270f79a4b6ef18f4bcead2b.zip | |
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
In preparation for changing how the driver handles 'mem_enable' in the CXL
DVSEC control register. Merge the contents of cxl_hdm_decode_init() into
cxl_dvsec_ranges() and rename the combined function cxl_hdm_decode_init().
The possible cleanups and fixes that result from this merge are saved for a
follow-on change.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/165291690027.1426646.10249756632415633752.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl/Kbuild')
| -rw-r--r-- | tools/testing/cxl/Kbuild | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 2ea6fcb8baa5..33543231d453 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -9,7 +9,7 @@ ldflags-y += --wrap=devm_cxl_setup_hdm ldflags-y += --wrap=devm_cxl_add_passthrough_decoder ldflags-y += --wrap=devm_cxl_enumerate_decoders ldflags-y += --wrap=cxl_await_media_ready -ldflags-y += --wrap=cxl_dvsec_ranges +ldflags-y += --wrap=cxl_hdm_decode_init DRIVERS := ../../../drivers CXL_SRC := $(DRIVERS)/cxl @@ -36,7 +36,6 @@ cxl_port-y += config_check.o obj-m += cxl_mem.o cxl_mem-y := $(CXL_SRC)/mem.o -cxl_mem-y += mock_mem.o cxl_mem-y += config_check.o obj-m += cxl_core.o |