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Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml new file mode 100644 index 000000000000..9212dfe6e956 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare Universal Multi-Protocol Memory Controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Manish Narani <manish.narani@xilinx.com> + - Michal Simek <michal.simek@xilinx.com> + +description: | + Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of + working with the memory devices supporting up to (LP)DDR4 protocol. It can + be equipped with SEC/DEC ECC feature if DRAM data bus width is either + 16-bits or 32-bits or 64-bits wide. + + For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a + controller. It has an optional SEC/DEC ECC support in 64- and 32-bits + bus width configurations. + +properties: + compatible: + oneOf: + - deprecated: true + description: Synopsys DW uMCTL2 DDR controller v3.80a + const: snps,ddrc-3.80a + - description: Synopsys DW uMCTL2 DDR controller + const: snps,dw-umctl2-ddrc + - description: Xilinx ZynqMP DDR controller v2.40a + const: xlnx,zynqmp-ddrc-2.40a + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0xfd070000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; +... |