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path: root/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
index 1a483d38e70d..1259b150dc96 100644
--- a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
@@ -84,6 +84,21 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0);
WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret);
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ uint32_t f32_offset, f32_cntl;
+
+ f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);
+ f32_cntl = RREG32(f32_offset);
+ f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);
+ f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);
+
+ adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;
+ adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
+
+ amdgpu_vpe_psp_update_sram(adev);
+ return 0;
+ }
+
vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
/* Thread 0(command thread) ucode offset/size */