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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index b99d2527cf03..9e38c37c1d73 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -169,14 +169,12 @@ struct dcn10_stream_enc_registers {
uint32_t DP_SEC_METADATA_TRANSMISSION;
uint32_t HDMI_METADATA_PACKET_CONTROL;
uint32_t DP_SEC_FRAMING4;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
uint32_t DP_GSP11_CNTL;
uint32_t HDMI_GENERIC_PACKET_CONTROL6;
uint32_t HDMI_GENERIC_PACKET_CONTROL7;
uint32_t HDMI_GENERIC_PACKET_CONTROL8;
uint32_t HDMI_GENERIC_PACKET_CONTROL9;
uint32_t HDMI_GENERIC_PACKET_CONTROL10;
-#endif
uint32_t DIG_CLOCK_PATTERN;
};
@@ -505,7 +503,6 @@ struct dcn10_stream_enc_registers {
type DP_PIXEL_COMBINE;\
type DP_SST_SDP_SPLITTING
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define SE_REG_FIELD_LIST_DCN3_0(type) \
type HDMI_GENERIC8_CONT;\
type HDMI_GENERIC8_SEND;\
@@ -531,22 +528,17 @@ struct dcn10_stream_enc_registers {
type DP_SEC_GSP11_PPS;\
type DP_SEC_GSP11_ENABLE;\
type DP_SEC_GSP11_LINE_NUM
-#endif
struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
SE_REG_FIELD_LIST_DCN2_0(uint8_t);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
SE_REG_FIELD_LIST_DCN3_0(uint8_t);
-#endif
};
struct dcn10_stream_encoder_mask {
SE_REG_FIELD_LIST_DCN1_0(uint32_t);
SE_REG_FIELD_LIST_DCN2_0(uint32_t);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
SE_REG_FIELD_LIST_DCN3_0(uint32_t);
-#endif
};
struct dcn10_stream_encoder {