diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_types.h | 57 |
1 files changed, 38 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3d4bf9b6a0a2..f6f0626649e0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -187,6 +187,21 @@ struct intel_encoder { * be set correctly before calling this function. */ void (*get_config)(struct intel_encoder *, struct intel_crtc_state *pipe_config); + + /* + * Optional hook called during init/resume to sync any state + * stored in the encoder (eg. DP link parameters) wrt. the HW state. + */ + void (*sync_state)(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); + + /* + * Optional hook, returning true if this encoder allows a fastset + * during the initial commit, false otherwise. + */ + bool (*initial_fastset_check)(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); + /* * Acquires the power domains needed for an active encoder during * hardware state readout. @@ -199,6 +214,11 @@ struct intel_encoder { * device interrupts are disabled. */ void (*suspend)(struct intel_encoder *); + /* + * Called during system reboot/shutdown after all the + * encoders have been disabled and suspended. + */ + void (*shutdown)(struct intel_encoder *encoder); enum hpd_pin hpd_pin; enum intel_display_power_domain power_domain; /* for communication with audio component; protected by av_mutex */ @@ -515,6 +535,7 @@ struct intel_plane_state { unsigned int rotation; enum drm_color_encoding color_encoding; enum drm_color_range color_range; + enum drm_scaling_filter scaling_filter; } hw; struct i915_ggtt_view view; @@ -805,6 +826,7 @@ struct intel_crtc_state { bool active, enable; struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; struct drm_display_mode mode, adjusted_mode; + enum drm_scaling_filter scaling_filter; } hw; /** @@ -1035,9 +1057,6 @@ struct intel_crtc_state { /* Output format RGB/YCBCR etc */ enum intel_output_format output_format; - /* Output down scaling is done in LSPCON device */ - bool lspcon_downsampling; - /* enable pipe gamma? */ bool gamma_enable; @@ -1183,6 +1202,9 @@ struct intel_plane { struct intel_plane_state *plane_state); int (*min_cdclk)(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); + void (*async_flip)(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state); }; struct intel_watermark_params { @@ -1270,7 +1292,6 @@ struct intel_dp { int link_rate; u8 lane_count; u8 sink_count; - bool link_mst; bool link_trained; bool has_hdmi_sink; bool has_audio; @@ -1280,6 +1301,8 @@ struct intel_dp { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; + u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; + u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; u8 fec_capable; /* source rates */ int num_source_rates; @@ -1312,8 +1335,6 @@ struct intel_dp { unsigned long last_backlight_off; ktime_t panel_power_off_time; - struct notifier_block edp_notifier; - /* * Pipe whose power sequencer is currently locked into * this port. Only relevant on VLV/CHV. @@ -1336,14 +1357,6 @@ struct intel_dp { bool is_mst; int active_mst_links; - /* - * DP_TP_* registers may be either on port or transcoder register space. - */ - struct { - i915_reg_t dp_tp_ctl; - i915_reg_t dp_tp_status; - } regs; - /* connector directly attached - won't be use for modeset in mst world */ struct intel_connector *attached_connector; @@ -1363,13 +1376,19 @@ struct intel_dp { i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); /* This is called before a link training is starterd */ - void (*prepare_link_retrain)(struct intel_dp *intel_dp); - void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat); - void (*set_idle_link_train)(struct intel_dp *intel_dp); - void (*set_signal_levels)(struct intel_dp *intel_dp); + void (*prepare_link_retrain)(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); + void (*set_link_train)(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + u8 dp_train_pat); + void (*set_idle_link_train)(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); + void (*set_signal_levels)(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); u8 (*preemph_max)(struct intel_dp *intel_dp); - u8 (*voltage_max)(struct intel_dp *intel_dp); + u8 (*voltage_max)(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); /* Displayport compliance testing */ struct intel_dp_compliance compliance; |