aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-omap2/sram34xx.S
AgeCommit message (Expand)AuthorFilesLines
2009-12-11OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behin...Gravatar Paul Walmsley 1-2/+17
2009-07-24OMAP3 SDRC: Move the clk stabilization delay to the right placeGravatar Rajendra Nayak 1-2/+2
2009-07-24OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83MhzGravatar Rajendra Nayak 1-1/+1
2009-07-24OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on bootGravatar Paul Walmsley 1-2/+0
2009-07-24OMAP3 SDRC: add support for 2 SDRAM chip selectsGravatar Jean Pihet 1-30/+107
2009-06-19OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLLGravatar Paul Walmsley 1-0/+12
2009-06-19OMAP3: Add support for DPLL3 divisor values higher than 2Gravatar Tero Kristo 1-3/+5
2009-06-19OMAP3 SRAM: convert SRAM code to use macros rather than magic numbersGravatar Paul Walmsley 1-15/+38
2009-06-19OMAP3 SRAM: add more comments on the SRAM codeGravatar Paul Walmsley 1-21/+24
2009-06-19OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock changeGravatar Paul Walmsley 1-1/+7
2009-06-19OMAP3 clock: add a short delay when lowering CORE clk rateGravatar Paul Walmsley 1-11/+9
2009-06-19OMAP3 clock: remove wait for DPLL3 M2 clock to stabilizeGravatar Paul Walmsley 1-3/+0
2009-05-12OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHzGravatar Paul Walmsley 1-6/+7
2009-05-12OMAP3 SRAM: renumber registers to make space for argument passingGravatar Paul Walmsley 1-57/+57
2009-05-12OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency changeGravatar Paul Walmsley 1-3/+4
2009-05-12OMAP3 clock: add interconnect barriers to CORE DPLL M2 changeGravatar Paul Walmsley 1-3/+6
2009-05-12OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpllGravatar Paul Walmsley 1-2/+2
2008-10-09ARM: OMAP3: Add minimal omap3430 supportGravatar Syed Mohammed, Khasim 1-0/+179