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path: root/arch/arm64/include/asm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2023-09-25arm64/sve: Remove SMCR pseudo register from cpufeature codeGravatar Mark Brown 1-3/+0
2023-09-25arm64/sve: Remove ZCR pseudo register from cpufeature codeGravatar Mark Brown 1-3/+0
2023-06-06arm64: cpufeature: add system register ID_AA64MMFR3Gravatar Joey Gouly 1-0/+1
2022-06-23arm64/sme: Expose SMIDR through sysfsGravatar Mark Brown 1-0/+1
2022-04-22arm64/sme: Identify supported SME vector lengths at bootGravatar Mark Brown 1-0/+3
2022-04-22arm64/sme: Basic enumeration supportGravatar Mark Brown 1-0/+1
2021-12-13arm64: add ID_AA64ISAR2_EL1 sys registerGravatar Joey Gouly 1-0/+1
2021-06-11arm64: cpuinfo: Split AArch32 registers out into a separate structGravatar Will Deacon 1-21/+25
2021-05-26arm64: Check if GMID_EL1.BS is the same on all CPUsGravatar Catalin Marinas 1-0/+1
2021-05-26arm64: Change the cpuinfo_arm64 member type for some sysregs to u64Gravatar Catalin Marinas 1-5/+5
2020-05-21arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 contextGravatar Anshuman Khandual 1-0/+1
2020-05-21arm64/cpufeature: Introduce ID_MMFR5 CPU registerGravatar Anshuman Khandual 1-0/+1
2020-05-21arm64/cpufeature: Introduce ID_DFR1 CPU registerGravatar Anshuman Khandual 1-0/+1
2020-05-21arm64/cpufeature: Introduce ID_PFR2 CPU registerGravatar Anshuman Khandual 1-0/+1
2020-01-15arm64: Introduce ID_ISAR6 CPU registerGravatar Anshuman Khandual 1-0/+1
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Gravatar Thomas Gleixner 1-12/+1
2017-11-03arm64/sve: Probe SVE capabilities and usable vector lengthsGravatar Dave Martin 1-0/+4
2016-07-12arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfsGravatar Steve Capper 1-0/+2
2016-02-18arm64: add ARMv8.2 id_aa64mmfr2 boiler plateGravatar James Morse 1-0/+1
2015-10-21arm64: Consolidate CPU Sanity check to CPU Feature infrastructureGravatar Suzuki K. Poulose 1-1/+2
2015-10-21arm64: Keep track of CPU feature registersGravatar Suzuki K. Poulose 1-0/+1
2015-10-21arm64: Move mixed endian support detectionGravatar Suzuki K. Poulose 1-0/+2
2015-01-07arm64: sanity checks: add missing AArch32 registersGravatar Mark Rutland 1-0/+5
2014-11-25arm64: sanity checks: add ID_AA64DFR{0,1}_EL1Gravatar Mark Rutland 1-0/+2
2014-07-18arm64: cpuinfo: record cpu system register valuesGravatar Mark Rutland 1-0/+59