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path: root/arch/mips/kernel/cpu-probe.c
AgeCommit message (Expand)AuthorFilesLines
2008-09-21[MIPS] Fix potential latency problem due to non-atomic cpu_wait.Gravatar Atsushi Nemoto 1-14/+2
2008-04-28[MIPS] Move arch/mips/philips to arch/mips/nxpGravatar Daniel Laird 1-4/+4
2008-04-28[MIPS] Add support for MIPS CMP platform.Gravatar Ralf Baechle 1-0/+5
2008-04-28[MIPS] Basic SPRAM supportGravatar Chris Dearman 1-0/+8
2008-03-12[MIPS] Fix loads of section missmatchesGravatar Ralf Baechle 1-5/+5
2008-01-29[MIPS] Alchemy: Au1210/Au1250 CPU supportGravatar Manuel Lauss 1-0/+9
2007-11-15[MIPS] Fix shadow register support.Gravatar Ralf Baechle 1-0/+5
2007-10-11[MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.Gravatar Franck Bui-Huu 1-0/+8
2007-10-11[MIPS] Make facility to convert CPU types to strings generally available.Gravatar Ralf Baechle 1-2/+91
2007-10-11[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Gravatar Ralf Baechle 1-8/+0
2007-10-11[MIPS] Add support for BCM47XX CPUs.Gravatar Aurelien Jarno 1-0/+20
2007-09-14[MIPS] 20Kc: Disable use of WAIT instruction.Gravatar Ralf Baechle 1-1/+8
2007-07-20[MIPS] Workaround for RM7000 WAIT instruction aka erratum 38Gravatar Ralf Baechle 1-1/+25
2007-07-10[MIPS] PMC MSP71xx mips commonGravatar Marc St-Jean 1-0/+20
2007-07-10[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Gravatar Fuxin Zhang 1-0/+8
2007-07-10[MIPS] Enable support for the userlocal hardware registerGravatar Ralf Baechle 1-0/+2
2007-07-06[MIPS] Fix scheduling latency issue on 24K, 34K and 74K coresGravatar Ralf Baechle 1-2/+13
2007-06-26[MIPS] 20K: Handle WAIT related bugs according to errata informationGravatar Ralf Baechle 1-1/+11
2007-02-20[MIPS] Make some __setup functions staticGravatar Atsushi Nemoto 1-1/+1
2007-02-18[MIPS] Include <asm/bugs> to for declaration of check_bugs32.Gravatar Ralf Baechle 1-0/+1
2007-02-06[MIPS] Whitespace cleanups.Gravatar Ralf Baechle 1-1/+1
2006-11-30[MIPS] Don't print presence of WAIT instruction on bootup.Gravatar Ralf Baechle 1-16/+3
2006-10-09[MIPS] Fix RM9000 wait instruction detection.Gravatar Ralf Baechle 1-1/+8
2006-09-27[MIPS] Reduce race between cpu_wait() and need_resched() checkingGravatar Atsushi Nemoto 1-17/+45
2006-07-13[MIPS] Save 2k text size in cpu-probeGravatar Thiemo Seufer 1-1/+1
2006-07-13[MIPS] Uses MIPS_CONF_AR instead of magic constants.Gravatar Thiemo Seufer 1-2/+2
2006-06-30Remove obsolete #include <linux/config.h>Gravatar Jörn Engel 1-1/+0
2006-06-29[MIPS] MIPS32/MIPS64 secondary cache managementGravatar Chris Dearman 1-2/+0
2006-06-06[MIPS] SB1: Only pass1 FPUs are broken beyond recovery.Gravatar Ralf Baechle 1-1/+1
2006-06-01[MIPS] Treat R14000 like R10000.Gravatar Kumba 1-0/+9
2006-06-01[MIPS] Fix detection and handling of the 74K processor.Gravatar Chris Dearman 1-0/+4
2006-03-21[MIPS] War on whitespace: cleanup initial spaces followed by tabs.Gravatar Ralf Baechle 1-3/+3
2006-02-07[MIPS] Get rid of CONFIG_SB1_PASS_1_WORKAROUNDS #ifdef crapola.Gravatar Ralf Baechle 1-4/+3
2006-01-10MIPS: Introduce machinery for testing for MIPSxxR1/2.Gravatar Ralf Baechle 1-5/+30
2006-01-10MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Gravatar Ralf Baechle 1-6/+6
2005-12-01[MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ...Gravatar Ralf Baechle 1-2/+2
2005-10-29Add support for SB1A CPU.Gravatar Andrew Isaacson 1-0/+3
2005-10-29Sibyte fixesGravatar Andrew Isaacson 1-1/+1
2005-10-29Detect 4KSD and treat it like 4KSc.Gravatar Ralf Baechle 1-0/+1
2005-10-29Cleanup the mess in cpu_cache_init.Gravatar Ralf Baechle 1-7/+18
2005-10-29R4600 has 32 FPRs.Gravatar Thiemo Seufer 1-1/+2
2005-10-29Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Gravatar Pete Popov 1-0/+19
2005-10-29Detect the MIPS R2 vectored interrupt, external interrupt controllerGravatar Ralf Baechle 1-0/+6
2005-10-29New kernel option nowait allows disabling the use of the wait instruction.Gravatar Ralf Baechle 1-0/+16
2005-10-29Detect the 34K.Gravatar Ralf Baechle 1-0/+5
2005-10-29For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style)Gravatar Maciej W. Rozycki 1-5/+1
2005-10-29Support the MIPS32 / MIPS64 DSP ASE.Gravatar Ralf Baechle 1-0/+3
2005-10-2964-bit fixes for Alchemy code ;)Gravatar Ralf Baechle 1-6/+5
2005-10-29No point in checking cpu_has_tlb before we've computed the CPU options.Gravatar Ralf Baechle 1-4/+4
2005-10-29Cleanup decoding of MIPSxx config registers.Gravatar Ralf Baechle 1-43/+98
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