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path: root/arch/mips/kernel/cpu-probe.c
AgeCommit message (Expand)AuthorFilesLines
2023-07-03MIPS: Loongson: Fix cpu_probe_loongson() againGravatar Huacai Chen 1-6/+3
2023-05-23MIPS: Restore Au1300 supportGravatar Manuel Lauss 1-0/+5
2023-04-05MIPS: Octeon: Opt-out 4k_cache featureGravatar Jiaxun Yang 1-0/+2
2022-07-14MIPS: Remove VR41xx supportGravatar Thomas Bogendoerfer 1-40/+0
2022-05-04MIPS: fix typos in commentsGravatar Julia Lawall 1-1/+1
2022-03-01MIPS: Remove TX39XX supportGravatar Thomas Bogendoerfer 1-23/+0
2021-11-25MIPS: loongson64: fix FTLB configurationGravatar Huang Pei 1-2/+2
2021-10-24MIPS: Remove NETLOGIC supportGravatar Thomas Bogendoerfer 1-84/+0
2021-06-01MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B)Gravatar Paul Cercueil 1-0/+5
2021-04-06MIPS: Loongson64: Use _CACHE_UNCACHED instead of _CACHE_UNCACHED_ACCELERATEDGravatar Tiezhu Yang 1-3/+0
2021-03-09MIPS: kernel: Reserve exception base early to prevent corruptionGravatar Thomas Bogendoerfer 1-0/+6
2021-01-22Revert "MIPS: Remove unused R4300 CPU support"Gravatar Lauri Kasanen 1-0/+9
2021-01-18MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs tooGravatar Paul Cercueil 1-7/+8
2020-10-12MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bitGravatar Thomas Bogendoerfer 1-6/+4
2020-10-12MIPS: cpu-probe: move fpu probing/handling into its own fileGravatar Thomas Bogendoerfer 1-324/+2
2020-09-18MIPS: cpu-probe: ingenic: Fix broken BUG_ONGravatar Paul Cercueil 1-1/+1
2020-09-18MIPS: cpu-probe: Mark XBurst CPU as having vtagged cachesGravatar Paul Cercueil 1-0/+3
2020-09-18MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WAGravatar Paul Cercueil 1-1/+2
2020-07-31MIPS: handle Loongson-specific GSExc exceptionGravatar WANG Xuerui 1-0/+3
2020-07-31MIPS: only register FTLBPar exception handler for supported modelsGravatar WANG Xuerui 1-0/+13
2020-07-24MIPS: X2000: Add X2000 system type.Gravatar 周琰杰 (Zhou Yanjie) 1-0/+11
2020-07-08MIPS: Unify naming style of vendor CP0.Config6 bitsGravatar Huacai Chen 1-6/+6
2020-06-04KVM: MIPS: Enable KVM support for Loongson-3Gravatar Huacai Chen 1-0/+1
2020-06-04KVM: MIPS: Introduce and use cpu_guest_has_ldpteGravatar Huacai Chen 1-1/+3
2020-05-24MIPS: emulate CPUCFG instruction on older Loongson64 coresGravatar WANG Xuerui 1-0/+9
2020-05-24MIPS: Tidy up CP0.Config6 bits definitionGravatar Huacai Chen 1-6/+6
2020-05-22mips: Add CP0 Write Merge config supportGravatar Serge Semin 1-0/+48
2020-05-22mips: Add MIPS Release 5 supportGravatar Serge Semin 1-0/+17
2020-05-07MIPS: Use fallthrough for arch/mipsGravatar Liangliang Huang 1-11/+11
2020-05-02MIPS: Loongson64: Correct TLB type for Loongson-3 ClassicGravatar Jiaxun Yang 1-1/+4
2020-04-30MIPS: Loongson64: Probe CPU features via CPUCFGGravatar Jiaxun Yang 1-8/+37
2020-04-26MIPS: Kernel: Identify Loongson-2K processorsGravatar Jiaxun Yang 1-1/+18
2020-03-19Use ELF_BASE_PLATFORM to pass ISA levelGravatar YunQiang Su 1-0/+18
2020-01-22MIPS: Add MAC2008 SupportGravatar Jiaxun Yang 1-1/+15
2020-01-09MIPS: X1830: Add X1830 system type.Gravatar 周琰杰 (Zhou Yanjie) 1-29/+36
2019-11-22MIPS: Ingenic: Disable abandoned HPTLB function.Gravatar Zhou Yanjie 1-2/+19
2019-11-11MIPS: Loongson: Rename LOONGSON1 to LOONGSON32Gravatar Huacai Chen 1-1/+1
2019-11-01Merge tag 'mips_fixes_5.4_3' into mips-nextGravatar Paul Burton 1-0/+33
2019-10-31MIPS: Loongson64: Rename CPU TYPESGravatar Jiaxun Yang 1-8/+8
2019-10-10MIPS: elf_hwcap: Export userspace ASEsGravatar Jiaxun Yang 1-0/+33
2019-10-07MIPS: Loongson: Add Loongson-3A R4 basic supportGravatar Huacai Chen 1-2/+14
2019-08-26MIPS: Treat Loongson Extensions as ASEsGravatar Jiaxun Yang 1-0/+6
2019-08-05MIPS: Ingenic: Disable broken BTB lookup optimization.Gravatar Zhou Yanjie 1-0/+7
2019-07-23MIPS: Remove unused R8000 CPU supportGravatar Paul Burton 1-9/+0
2019-07-23MIPS: Remove unused R5432 CPU supportGravatar Paul Burton 1-8/+0
2019-07-23MIPS: Remove unused R4300 CPU supportGravatar Paul Burton 1-9/+0
2019-07-21MIPS: Decode config3 register on Ingenic SoCsGravatar Paul Cercueil 1-0/+8
2019-07-21MIPS: Rename JZRISC to XBURSTGravatar Paul Cercueil 1-3/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Gravatar Thomas Gleixner 1-5/+1
2019-05-09MIPS: Fix Ingenic SoCs sometimes reporting wrong ISAGravatar Paul Cercueil 1-0/+8