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path: root/arch/riscv/kernel/cpu.c
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2023-09-01Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Gravatar Linus Torvalds 1-118/+63
2023-08-08riscv: Fix CPU feature detection with SMP disabledGravatar Samuel Holland 1-0/+5
2023-08-02RISC-V: cpu: refactor deprecated strncpyGravatar Justin Stitt 1-6/+6
2023-07-25RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa"Gravatar Conor Dooley 1-1/+7
2023-07-25RISC-V: try new extension properties in of_early_processor_hartid()Gravatar Conor Dooley 1-1/+28
2023-07-25RISC-V: add single letter extensions to riscv_isa_extGravatar Conor Dooley 1-26/+11
2023-07-25RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()Gravatar Conor Dooley 1-2/+3
2023-07-25RISC-V: shunt isa_ext_arr to cpufeature.cGravatar Conor Dooley 1-73/+2
2023-07-25RISC-V: drop a needless check in print_isa_ext()Gravatar Conor Dooley 1-4/+0
2023-07-25RISC-V: don't parse dt/acpi isa string to get rv32/rv64Gravatar Heiko Stuebner 1-12/+9
2023-07-25RISC-V: Provide a more helpful error message on invalid ISA stringsGravatar Palmer Dabbelt 1-2/+6
2023-06-23Merge patch series "ISA string parser cleanups"Gravatar Palmer Dabbelt 1-4/+30
2023-06-21RISC-V: always report presence of extensions formerly part of the base ISAGravatar Conor Dooley 1-0/+4
2023-06-21RISC-V: validate riscv,isa at boot, not during ISA string parsingGravatar Conor Dooley 1-3/+5
2023-06-21RISC-V: split early & late of_node to hartid mappingGravatar Conor Dooley 1-1/+21
2023-06-19Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe"Gravatar Palmer Dabbelt 1-0/+2
2023-06-19RISC-V: Add Zba, Zbs extension probingGravatar Evan Green 1-0/+2
2023-06-06Merge patch series "riscv: allow case-insensitive ISA string parsing"Gravatar Palmer Dabbelt 1-1/+2
2023-06-06riscv: allow case-insensitive ISA string parsingGravatar Yangyu Chen 1-1/+2
2023-06-01RISC-V: cpu: Enable cpuinfo for ACPI systemsGravatar Sunil V L 1-8/+22
2023-05-05Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEADGravatar Paolo Bonzini 1-0/+2
2023-04-21RISC-V: Detect AIA CSRs from ISA stringGravatar Anup Patel 1-0/+2
2023-04-18Merge patch series "RISC-V Hardware Probing User Interface"Gravatar Palmer Dabbelt 1-6/+2
2023-04-18RISC-V: Move struct riscv_cpuinfo to new headerGravatar Evan Green 1-6/+2
2023-03-15Merge patch series "RISC-V: Apply Zicboz to clear_page"Gravatar Palmer Dabbelt 1-0/+1
2023-03-14RISC-V: Add Zicboz detection and block size parsingGravatar Andrew Jones 1-0/+1
2023-03-09Merge patch series "riscv, mm: detect svnapot cpu support at runtime"Gravatar Palmer Dabbelt 1-0/+1
2023-03-07riscv: mm: modify pte format for SvnapotGravatar Qinglin Pan 1-0/+1
2023-02-21RISC-V: fix ordering of Zbb extensionGravatar Heiko Stuebner 1-1/+1
2023-01-31RISC-V: add zbb support to string functionsGravatar Heiko Stuebner 1-0/+1
2023-01-19Merge patch series "Putting some basic order on isa extension lists"Gravatar Palmer Dabbelt 1-15/+38
2023-01-17RISC-V: resort all extensions in consistent ordersGravatar Conor Dooley 1-2/+2
2023-01-17RISC-V: clarify ISA string ordering rules in cpu.cGravatar Conor Dooley 1-13/+36
2022-12-14Merge tag 'riscv-for-linus-6.2-mw1' of git://git.kernel.org/pub/scm/linux/ker...Gravatar Linus Torvalds 1-3/+27
2022-10-27RISC-V: Fix /proc/cpuinfo cpumask warningGravatar Andrew Jones 1-0/+3
2022-10-27RISC-V: Cache SBI vendor valuesGravatar Heiko Stuebner 1-3/+27
2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Gravatar Linus Torvalds 1-0/+51
2022-10-13RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputGravatar Palmer Dabbelt 1-0/+51
2022-10-11Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmGravatar Linus Torvalds 1-0/+1
2022-10-06RISC-V: Print SSTC in canonical orderGravatar Palmer Dabbelt 1-1/+1
2022-10-03RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo outputGravatar Anup Patel 1-0/+51
2022-10-02RISC-V: Probe Svinval extension form ISA stringGravatar Mayuresh Chitale 1-0/+1
2022-08-11RISC-V: Add Sstc extension supportGravatar Palmer Dabbelt 1-0/+1
2022-08-11RISC-V: Enable sstc extension parsing from DTGravatar Atish Patra 1-0/+1
2022-08-11arch/riscv: add Zihintpause supportGravatar Dao Lu 1-0/+1
2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantGravatar Palmer Dabbelt 1-0/+1
2022-07-28riscv: Add support for non-coherent devices using zicbom extensionGravatar Heiko Stuebner 1-0/+1
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Gravatar Sunil V L 1-11/+15
2022-05-21riscv: Don't output a bogus mmu-type on a no MMU kernelGravatar Niklas Cassel 1-0/+4
2022-05-11riscv: add RISC-V Svpbmt extension supportGravatar Heiko Stuebner 1-0/+1