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AgeCommit message (Expand)AuthorFilesLines
2023-08-31riscv: remove redundant mv instructionsGravatar Nam Cao 1-5/+1
2023-06-08riscv: prevent stack corruption by reserving task_pt_regs(p) earlyGravatar Greentime Hu 1-0/+2
2023-06-08riscv: Disable Vector Instructions for kernel itselfGravatar Guo Ren 1-6/+6
2023-06-08riscv: Clear vector regfile on bootupGravatar Greentime Hu 1-2/+25
2023-01-19riscv: fix -Wundef warning for CONFIG_RISCV_BOOT_SPINWAITGravatar Masahiro Yamada 1-1/+1
2022-06-01riscv: Initialize thread pointer before calling C functionsGravatar Alexandre Ghiti 1-0/+1
2022-05-25RISC-V: Split out the XIP fixups into their own fileGravatar Palmer Dabbelt 1-0/+1
2022-03-10RISC-V: Add arch functions for non-retentive suspend entry/exitGravatar Anup Patel 1-21/+0
2022-03-10RISC-V: Rename relocate() and make it globalGravatar Anup Patel 1-3/+4
2022-01-20RISC-V: Move spinwait booting method to its own configGravatar Atish Patra 1-4/+4
2022-01-20RISC-V: Move the entire hart selection via lottery to SMPGravatar Atish Patra 1-2/+6
2022-01-20RISC-V: Use __cpu_up_stack/task_pointer only for spinwait methodGravatar Atish Patra 1-2/+2
2022-01-20RISC-V: Avoid using per cpu array for ordered bootingGravatar Atish Patra 1-9/+10
2022-01-19RISC-V: Introduce sv48 support without relocatable kernelGravatar Palmer Dabbelt 1-1/+2
2022-01-19riscv: Implement sv48 supportGravatar Alexandre Ghiti 1-1/+2
2022-01-09riscv: head: remove useless __PAGE_ALIGNED_BSS and .balignGravatar Jisheng Zhang 1-4/+0
2022-01-09riscv: head: make secondary_start_common() staticGravatar Jisheng Zhang 1-3/+2
2022-01-07riscv/head: fix misspelling of guaranteedGravatar hasheddan 1-1/+1
2021-11-13Merge tag 'riscv-for-linus-5.16-mw1' of git://git.kernel.org/pub/scm/linux/ke...Gravatar Linus Torvalds 1-0/+12
2021-11-01Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu...Gravatar Linus Torvalds 1-1/+0
2021-10-27riscv: fix misalgned trap vector base addressGravatar Chen Lu 1-0/+1
2021-10-26riscv: remove .text section size limitation for XIPGravatar Vitaly Wool 1-0/+12
2021-09-30riscv: rely on core code to keep thread_info::cpu updatedGravatar Ard Biesheuvel 1-1/+0
2021-07-05riscv: Introduce structure that group all variables regarding kernel mappingGravatar Alexandre Ghiti 1-2/+2
2021-04-26RISC-V: enable XIPGravatar Vitaly Wool 1-1/+45
2021-04-26riscv: Move kernel mapping outside of linear mappingGravatar Alexandre Ghiti 1-1/+2
2021-02-18riscv: add BUILTIN_DTB support for MMU-enabled targetsGravatar Vitaly Wool 1-0/+4
2020-12-18Merge tag 'riscv-for-linus-5.11-mw0' of git://git.kernel.org/pub/scm/linux/ke...Gravatar Linus Torvalds 1-1/+0
2020-11-25riscv: Enable ARCH_STACKWALKGravatar Kefeng Wang 1-1/+0
2020-11-05riscv: Set text_offset correctly for M-ModeGravatar Sean Anderson 1-0/+5
2020-10-02RISC-V: Add PE/COFF header for EFI stubGravatar Atish Patra 1-0/+16
2020-10-02RISC-V: Move DT mapping outof fixmapGravatar Anup Patel 1-1/+0
2020-09-15RISC-V: Fix duplicate included thread_info.hGravatar Tian Tao 1-1/+0
2020-08-14riscv: Setup exception vector for nommu platformGravatar Qiu Wenbo 1-8/+17
2020-07-30RISC-V: Setup exception vector earlyGravatar Atish Patra 1-2/+8
2020-05-18RISC-V: Skip setting up PMPs on trapsGravatar Palmer Dabbelt 1-1/+10
2020-04-03riscv: Add SOC early init supportGravatar Damien Le Moal 1-0/+1
2020-03-31RISC-V: Add supported for ordered booting method using HSMGravatar Atish Patra 1-0/+26
2020-03-31RISC-V: Move relocate and few other functions out of __initGravatar Atish Patra 1-71/+82
2020-02-18riscv: set pmp configuration if kernel is running in M-modeGravatar Greentime Hu 1-0/+6
2020-01-22riscv: Add KASAN supportGravatar Nick Hu 1-0/+3
2020-01-15riscv: make sure the cores stay looping in .Lsecondary_parkGravatar Greentime Hu 1-6/+10
2020-01-12riscv: Fixup obvious bug for fp-regs resetGravatar Guo Ren 1-1/+1
2019-12-20riscv: fix scratch register clearing in M-mode.Gravatar Greentime Hu 1-1/+1
2019-11-17riscv: add nommu supportGravatar Christoph Hellwig 1-0/+6
2019-11-17riscv: clear the instruction cache and all registers when bootingGravatar Christoph Hellwig 1-1/+87
2019-11-17riscv: read the hart ID from mhartid on bootGravatar Damien Le Moal 1-0/+8
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeGravatar Christoph Hellwig 1-6/+6
2019-09-20arch/riscv: disable excess harts before picking main boot hartGravatar Xiang Wang 1-3/+5
2019-09-16Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Gravatar Linus Torvalds 1-1/+1