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path: root/arch/x86/events/rapl.c
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2023-10-08perf/x86/rapl: Annotate 'struct rapl_pmus' with __counted_byGravatar Kees Cook 1-1/+1
2023-10-03perf/x86/rapl: Fix "Using plain integer as NULL pointer" Sparse warningGravatar David Reaver 1-4/+4
2023-10-03perf/x86/rapl: Use local64_try_cmpxchg in rapl_event_update()Gravatar Uros Bizjak 1-6/+4
2023-10-03perf/x86/rapl: Stop doing cpu_relax() in the local64_cmpxchg() loop in rapl_e...Gravatar Uros Bizjak 1-3/+1
2023-08-09x86/cpu: Fix Gracemont uarchGravatar Peter Zijlstra 1-1/+1
2023-01-04perf/x86/rapl: Add support for Intel Emerald RapidsGravatar Zhang Rui 1-0/+1
2023-01-04perf/x86/rapl: Add support for Intel Meteor LakeGravatar Zhang Rui 1-0/+2
2023-01-03perf/x86/rapl: Treat Tigerlake like IcelakeGravatar Chris Wilson 1-0/+2
2022-11-02perf/x86/rapl: Use standard Energy Unit for SPR Dram RAPL domainGravatar Zhang Rui 1-5/+1
2022-10-27perf/x86/rapl: Add support for Intel Raptor LakeGravatar Zhang Rui 1-0/+3
2022-10-27perf/x86/rapl: Add support for Intel AlderLake-NGravatar Zhang Rui 1-0/+1
2022-01-18perf/x86/rapl: fix AMD event handlingGravatar Stephane Eranian 1-3/+6
2021-06-01perf/x86/rapl: Use CPUID bit on AMD and Hygon partsGravatar Andrew Cooper 1-4/+2
2021-04-19perf/x86/rapl: Add support for Intel Alder LakeGravatar Zhang Rui 1-0/+2
2021-02-10perf/x86/rapl: Fix psys-energy event on Intel SPR platformGravatar Zhang Rui 1-12/+9
2021-02-10perf/x86/rapl: Only check lower 32bits for RAPL energy countersGravatar Zhang Rui 1-5/+8
2020-11-17perf/x86: fix sysfs type mismatchesGravatar Sami Tolvanen 1-13/+1
2020-09-10perf/x86/rapl: Add AMD Fam19h RAPL supportGravatar Kim Phillips 1-0/+1
2020-08-14perf/x86/rapl: Add support for Intel SPR platformGravatar Zhang Rui 1-0/+20
2020-08-14perf/x86/rapl: Support multiple RAPL unit quirksGravatar Zhang Rui 1-9/+15
2020-08-14perf/x86/rapl: Fix missing psys sysfs attributesGravatar Zhang Rui 1-1/+1
2020-07-28perf/x86/rapl: Add Hygon Fam18h RAPL supportGravatar Pu Wen 1-1/+2
2020-05-28perf/x86/rapl: Add AMD Fam17h RAPL supportGravatar Stephane Eranian 1-0/+18
2020-05-28perf/x86/rapl: Flip logic on default events visibilityGravatar Stephane Eranian 1-0/+11
2020-05-28perf/x86/rapl: Refactor to share the RAPL code between Intel and AMD CPUsGravatar Stephane Eranian 1-6/+23
2020-05-28perf/x86/rapl: Move RAPL support to common x86 codeGravatar Stephane Eranian 1-0/+805
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