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path: root/drivers/clk/clk-versaclock5.c
AgeCommit message (Expand)AuthorFilesLines
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Gravatar Thomas Gleixner 1-10/+1
2019-01-09clk: vc5: Abort clock configuration without upstream clockGravatar Marek Vasut 1-1/+3
2018-12-14clk: vc5: Add suspend/resume supportGravatar Marek Vasut 1-0/+25
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Gravatar Vladimir Barinov 1-0/+11
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Gravatar Marek Vasut 1-0/+11
2017-07-17clk: vc5: Add support for the input frequency doublerGravatar Marek Vasut 1-1/+77
2017-07-17clk: vc5: Split clock input mux and predividerGravatar Marek Vasut 1-12/+34
2017-07-17clk: vc5: Configure the output buffer input mux on prepareGravatar Marek Vasut 1-0/+19
2017-07-17clk: vc5: Do not warn about disabled output buffer input muxesGravatar Marek Vasut 1-0/+3
2017-07-17clk: vc5: Fix trivial typoGravatar Marek Vasut 1-1/+1
2017-07-17clk: vc5: Prevent division by zero on unconfigured outputsGravatar Marek Vasut 1-0/+4
2017-04-19clk: vc5: Add support for IDT VersaClock 5P49V5935Gravatar Alexey Firago 1-2/+13
2017-04-19clk: vc5: Add structure to describe particular chip featuresGravatar Alexey Firago 1-18/+47
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Gravatar Marek Vasut 1-0/+791