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path: root/drivers/clk/clk-versaclock5.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-18clk: vc5: Add support for 5P49V60Gravatar Lars-Peter Clausen 1-3/+22
2023-01-18clk: vc5: Use `clamp()` to restrict PLL rangeGravatar Lars-Peter Clausen 1-4/+1
2022-11-22clk: Remove a useless includeGravatar Christophe JAILLET 1-1/+0
2022-10-08Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Gravatar Linus Torvalds 1-58/+105
2022-10-04Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' i...Gravatar Stephen Boyd 1-57/+104
2022-10-03clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975Gravatar Matthias Fend 1-0/+11
2022-09-30clk: vc5: Use regmap_{set,clear}_bits() where appropriateGravatar Lars-Peter Clausen 1-20/+15
2022-09-30clk: vc5: Check IO access resultsGravatar Lars-Peter Clausen 1-50/+91
2022-09-30clk: vc5: Fix 5P49V6901 outputs disabling when enabling FODGravatar Serge Semin 1-1/+1
2022-08-22dt-bindings: clock: Move versaclock.h to dt-bindings/clockGravatar Lukas Bulwahn 1-1/+1
2022-08-16i2c: Make remove callback return voidGravatar Uwe Kleine-König 1-3/+1
2021-11-02clk: vc5: Use i2c .probe_newGravatar Luca Ceresoli 1-2/+2
2021-08-28clk: vc5: Add properties for configuring SD/OE behaviorGravatar Sean Anderson 1-0/+24
2021-08-28clk: vc5: Use dev_err_probeGravatar Sean Anderson 1-10/+10
2021-06-08clk: vc5: fix output disabling when enabling a FODGravatar Luca Ceresoli 1-3/+24
2021-02-11clk: vc5: Add support for optional load capacitanceGravatar Adam Ford 1-0/+64
2020-12-19clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"Gravatar Geert Uytterhoeven 1-2/+2
2020-07-23clk: vc5: use a dedicated struct to describe the output driversGravatar Luca Ceresoli 1-9/+15
2020-07-22clk: vc5: Add memory check to prevent oopsGravatar Adam Ford 1-3/+5
2020-07-22clk: vc5: fix use of memory after it has been kfree'dGravatar Colin Ian King 1-32/+18
2020-06-22clk: vc5: Enable addition output configurations of the VersaclockGravatar Adam Ford 1-0/+156
2020-06-22clk: vc5: Allow Versaclock driver to support multiple instancesGravatar Adam Ford 1-47/+37
2020-05-30clk: vc5: Add support for IDT VersaClock 5P49V6965Gravatar Adam Ford 1-0/+11
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Gravatar Thomas Gleixner 1-10/+1
2019-01-09clk: vc5: Abort clock configuration without upstream clockGravatar Marek Vasut 1-1/+3
2018-12-14clk: vc5: Add suspend/resume supportGravatar Marek Vasut 1-0/+25
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Gravatar Vladimir Barinov 1-0/+11
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Gravatar Marek Vasut 1-0/+11
2017-07-17clk: vc5: Add support for the input frequency doublerGravatar Marek Vasut 1-1/+77
2017-07-17clk: vc5: Split clock input mux and predividerGravatar Marek Vasut 1-12/+34
2017-07-17clk: vc5: Configure the output buffer input mux on prepareGravatar Marek Vasut 1-0/+19
2017-07-17clk: vc5: Do not warn about disabled output buffer input muxesGravatar Marek Vasut 1-0/+3
2017-07-17clk: vc5: Fix trivial typoGravatar Marek Vasut 1-1/+1
2017-07-17clk: vc5: Prevent division by zero on unconfigured outputsGravatar Marek Vasut 1-0/+4
2017-04-19clk: vc5: Add support for IDT VersaClock 5P49V5935Gravatar Alexey Firago 1-2/+13
2017-04-19clk: vc5: Add structure to describe particular chip featuresGravatar Alexey Firago 1-18/+47
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Gravatar Marek Vasut 1-0/+791